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282ec57c4c
an appropriate TargetRegisterClass, also adds TargetRegisterClass definition. TargetMachine.h - speling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4781 91177308-0d34-0410-b5e6-96231b3b80d8
131 lines
4.7 KiB
C++
131 lines
4.7 KiB
C++
//===- Target/MRegisterInfo.h - Target Register Information -------*-C++-*-===//
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//
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// This file describes an abstract interface used to get information about a
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// target machines register file. This information is used for a variety of
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// purposed, especially register allocation.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_MREGISTERINFO_H
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#define LLVM_TARGET_MREGISTERINFO_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include <assert.h>
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class Type;
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/// MRegisterDesc - This record contains all of the information known about a
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/// particular register.
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///
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struct MRegisterDesc {
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const char *Name; // Assembly language name for the register
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unsigned Flags; // Flags identifying register properties (defined below)
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unsigned TSFlags; // Target Specific Flags
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};
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/// MRF namespace - This namespace contains flags that pertain to machine
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/// registers
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///
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namespace MRF { // MRF = Machine Register Flags
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enum {
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INT8 = 1 << 0, // This is an 8 bit integer register
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INT16 = 1 << 1, // This is a 16 bit integer register
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INT32 = 1 << 2, // This is a 32 bit integer register
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INT64 = 1 << 3, // This is a 64 bit integer register
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INT128 = 1 << 4, // This is a 128 bit integer register
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FP32 = 1 << 5, // This is a 32 bit floating point register
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FP64 = 1 << 6, // This is a 64 bit floating point register
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FP80 = 1 << 7, // This is a 80 bit floating point register
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FP128 = 1 << 8, // This is a 128 bit floating point register
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};
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};
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class TargetRegisterClass {
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protected:
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TargetRegisterClass() {}
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public:
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typedef unsigned* iterator;
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typedef unsigned* const_iterator;
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iterator begin();
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iterator end();
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const_iterator begin() const;
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const_iterator end() const;
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virtual unsigned getNumRegs() const { return 0; }
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virtual unsigned getRegister(unsigned idx) const { return 0; }
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virtual unsigned getDataSize() const { return 0; }
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//const std::vector<unsigned> &getRegsInClass(void) { return Regs; }
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//void getAliases(void);
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};
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/// MRegisterInfo base class - We assume that the target defines a static array
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/// of MRegisterDesc objects that represent all of the machine registers that
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/// the target has. As such, we simply have to track a pointer to this array so
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/// that we can turn register number into a register descriptor.
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///
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class MRegisterInfo {
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const MRegisterDesc *Desc; // Pointer to the descriptor array
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unsigned NumRegs; // Number of entries in the array
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protected:
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MRegisterInfo(const MRegisterDesc *D, unsigned NR) : Desc(D), NumRegs(NR) {}
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public:
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enum { // Define some target independant constants
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/// NoRegister - This 'hard' register is a 'noop' register for all backends.
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/// This is used as the destination register for instructions that do not
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/// produce a value. Some frontends may use this as an operand register to
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/// mean special things, for example, the Sparc backend uses R0 to mean %g0
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/// which always PRODUCES the value 0. The X86 backend does not use this
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/// value as an operand register.
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///
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NoRegister = 0,
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/// FirstVirtualRegister - This is the first register number that is
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/// considered to be a 'virtual' register, which is part of the SSA
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/// namespace. This must be the same for all targets, which means that each
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/// target is limited to 1024 registers.
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///
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FirstVirtualRegister = 1024,
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};
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const MRegisterDesc &operator[](unsigned RegNo) const {
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assert(RegNo < NumRegs &&
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"Attempting to access record for invalid register number!");
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return Desc[RegNo];
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}
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/// Provide a get method, equivalent to [], but more useful if we have a
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/// pointer to this object.
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///
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const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
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virtual void copyReg2PCRel(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned SrcReg, unsigned ImmOffset,
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unsigned dataSize) const = 0;
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virtual void copyPCRel2Reg(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned ImmOffset, unsigned DestReg,
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unsigned dataSize) const = 0;
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/// Register class iterators
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typedef const TargetRegisterClass* const_iterator;
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virtual const_iterator const_regclass_begin() const = 0;
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virtual const_iterator const_regclass_end() const = 0;
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virtual unsigned getNumRegClasses() const = 0;
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virtual const TargetRegisterClass* getRegClassForType(const Type* Ty) const=0;
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};
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#endif
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