mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8
296 lines
9.4 KiB
C++
296 lines
9.4 KiB
C++
//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsInstrInfo.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "MipsGenInstrInfo.inc"
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// Pin the vtable to this file.
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void MipsInstrInfo::anchor() {}
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MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
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: MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
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TM(tm), UncondBrOpc(UncondBr) {}
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const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) {
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if (TM.getSubtargetImpl()->inMips16Mode())
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return llvm::createMips16InstrInfo(TM);
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return llvm::createMipsSEInstrInfo(TM);
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}
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bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
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return op.isImm() && op.getImm() == 0;
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}
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/// insertNoop - If data hazard condition is found insert the target nop
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/// instruction.
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void MipsInstrInfo::
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insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
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{
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DebugLoc DL;
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BuildMI(MBB, MI, DL, get(Mips::NOP));
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}
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MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
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unsigned Flag) const {
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FI);
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return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
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MFI.getObjectSize(FI), Align);
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
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MachineBasicBlock *&BB,
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
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int NumOp = Inst->getNumExplicitOperands();
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// for both int and fp branches, the last explicit operand is the
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// MBB.
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BB = Inst->getOperand(NumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(Opc));
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for (int i=0; i<NumOp-1; i++)
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Cond.push_back(Inst->getOperand(i));
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}
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bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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SmallVector<MachineInstr*, 2> BranchInstrs;
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BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
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return (BT == BT_None) || (BT == BT_Indirect);
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}
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void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB, DebugLoc DL,
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const SmallVectorImpl<MachineOperand>& Cond)
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const {
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unsigned Opc = Cond[0].getImm();
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const MCInstrDesc &MCID = get(Opc);
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MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
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for (unsigned i = 1; i < Cond.size(); ++i) {
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if (Cond[i].isReg())
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MIB.addReg(Cond[i].getReg());
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else if (Cond[i].isImm())
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MIB.addImm(Cond[i].getImm());
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else
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assert(true && "Cannot copy operand");
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}
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MIB.addMBB(TBB);
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}
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unsigned MipsInstrInfo::
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InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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// # of condition operands:
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// Unconditional branches: 0
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// Floating point branches: 1 (opc)
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// Int BranchZero: 2 (opc, reg)
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// Int Branch: 3 (opc, reg0, reg1)
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assert((Cond.size() <= 3) &&
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"# of Mips branch conditions must be <= 3!");
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// Two-way Conditional branch.
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if (FBB) {
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BuildCondBr(MBB, TBB, DL, Cond);
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BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
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return 2;
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}
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// One way branch.
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// Unconditional branch.
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if (Cond.empty())
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BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
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else // Conditional branch.
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BuildCondBr(MBB, TBB, DL, Cond);
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return 1;
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}
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unsigned MipsInstrInfo::
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RemoveBranch(MachineBasicBlock &MBB) const
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{
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
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MachineBasicBlock::reverse_iterator FirstBr;
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unsigned removed;
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// Skip all the debug instructions.
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while (I != REnd && I->isDebugValue())
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++I;
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FirstBr = I;
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// Up to 2 branches are removed.
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// Note that indirect branches are not removed.
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for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
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if (!getAnalyzableBrOpc(I->getOpcode()))
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break;
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MBB.erase(I.base(), FirstBr.base());
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return removed;
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}
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/// ReverseBranchCondition - Return the inverse opcode of the
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/// specified Branch instruction.
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bool MipsInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
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{
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assert( (Cond.size() && Cond.size() <= 3) &&
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"Invalid Mips branch condition!");
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Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
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return false;
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}
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MipsInstrInfo::BranchType MipsInstrInfo::
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AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify,
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SmallVectorImpl<MachineInstr*> &BranchInstrs) const {
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
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// Skip all the debug instructions.
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while (I != REnd && I->isDebugValue())
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++I;
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if (I == REnd || !isUnpredicatedTerminator(&*I)) {
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// This block ends with no branches (it just falls through to its succ).
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// Leave TBB/FBB null.
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TBB = FBB = nullptr;
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return BT_NoBranch;
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}
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MachineInstr *LastInst = &*I;
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unsigned LastOpc = LastInst->getOpcode();
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BranchInstrs.push_back(LastInst);
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// Not an analyzable branch (e.g., indirect jump).
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if (!getAnalyzableBrOpc(LastOpc))
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return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
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// Get the second to last instruction in the block.
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unsigned SecondLastOpc = 0;
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MachineInstr *SecondLastInst = nullptr;
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if (++I != REnd) {
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SecondLastInst = &*I;
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SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
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// Not an analyzable branch (must be an indirect jump).
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if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
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return BT_None;
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}
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// If there is only one terminator instruction, process it.
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if (!SecondLastOpc) {
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// Unconditional branch.
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if (LastOpc == UncondBrOpc) {
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TBB = LastInst->getOperand(0).getMBB();
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return BT_Uncond;
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}
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// Conditional branch
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AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
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return BT_Cond;
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}
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// If we reached here, there are two branches.
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// If there are three terminators, we don't know what sort of block this is.
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if (++I != REnd && isUnpredicatedTerminator(&*I))
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return BT_None;
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BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
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// If second to last instruction is an unconditional branch,
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// analyze it and remove the last instruction.
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if (SecondLastOpc == UncondBrOpc) {
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// Return if the last instruction cannot be removed.
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if (!AllowModify)
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return BT_None;
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TBB = SecondLastInst->getOperand(0).getMBB();
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LastInst->eraseFromParent();
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BranchInstrs.pop_back();
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return BT_Uncond;
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}
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// Conditional branch followed by an unconditional branch.
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// The last one must be unconditional.
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if (LastOpc != UncondBrOpc)
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return BT_None;
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AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
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FBB = LastInst->getOperand(0).getMBB();
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return BT_CondUncond;
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}
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/// Return the number of bytes of code the specified instruction may be.
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unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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default:
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return MI->getDesc().getSize();
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case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
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const MachineFunction *MF = MI->getParent()->getParent();
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const char *AsmStr = MI->getOperand(0).getSymbolName();
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return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
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}
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case Mips::CONSTPOOL_ENTRY:
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// If this machine instr is a constant pool entry, its size is recorded as
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// operand #2.
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return MI->getOperand(2).getImm();
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}
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}
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MachineInstrBuilder
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MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
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MachineBasicBlock::iterator I) const {
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MachineInstrBuilder MIB;
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MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
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for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J)
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MIB.addOperand(I->getOperand(J));
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MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
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return MIB;
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}
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