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https://github.com/c64scene-ar/llvm-6502.git
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181b9c6a2a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26625 91177308-0d34-0410-b5e6-96231b3b80d8
587 lines
17 KiB
Plaintext
587 lines
17 KiB
Plaintext
//===---------------------------------------------------------------------===//
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// Random ideas for the X86 backend.
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//===---------------------------------------------------------------------===//
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Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
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Hi and Lo parts (combination of MUL and MULH[SU] into one node). Add this to
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X86, & make the dag combiner produce it when needed. This will eliminate one
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imul from the code generated for:
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long long test(long long X, long long Y) { return X*Y; }
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by using the EAX result from the mul. We should add a similar node for
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DIVREM.
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another case is:
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long long test(int X, int Y) { return (long long)X*Y; }
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... which should only be one imul instruction.
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//===---------------------------------------------------------------------===//
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This should be one DIV/IDIV instruction, not a libcall:
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unsigned test(unsigned long long X, unsigned Y) {
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return X/Y;
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}
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This can be done trivially with a custom legalizer. What about overflow
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though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
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//===---------------------------------------------------------------------===//
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Some targets (e.g. athlons) prefer freep to fstp ST(0):
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http://gcc.gnu.org/ml/gcc-patches/2004-04/msg00659.html
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//===---------------------------------------------------------------------===//
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This should use fiadd on chips where it is profitable:
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double foo(double P, int *I) { return P+*I; }
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We have fiadd patterns now but the followings have the same cost and
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complexity. We need a way to specify the later is more profitable.
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def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fadd RFP:$src1,
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(extloadf64f32 addr:$src2)))]>;
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// ST(0) = ST(0) + [mem32]
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def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fadd RFP:$src1,
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(X86fild addr:$src2, i32)))]>;
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// ST(0) = ST(0) + [mem32int]
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//===---------------------------------------------------------------------===//
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The FP stackifier needs to be global. Also, it should handle simple permutates
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to reduce number of shuffle instructions, e.g. turning:
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fld P -> fld Q
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fld Q fld P
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fxch
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or:
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fxch -> fucomi
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fucomi jl X
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jg X
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Ideas:
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http://gcc.gnu.org/ml/gcc-patches/2004-11/msg02410.html
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//===---------------------------------------------------------------------===//
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Improvements to the multiply -> shift/add algorithm:
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http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
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//===---------------------------------------------------------------------===//
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Improve code like this (occurs fairly frequently, e.g. in LLVM):
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long long foo(int x) { return 1LL << x; }
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
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Another useful one would be ~0ULL >> X and ~0ULL << X.
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//===---------------------------------------------------------------------===//
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Compile this:
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_Bool f(_Bool a) { return a!=1; }
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into:
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movzbl %dil, %eax
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xorl $1, %eax
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ret
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//===---------------------------------------------------------------------===//
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Some isel ideas:
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1. Dynamic programming based approach when compile time if not an
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issue.
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2. Code duplication (addressing mode) during isel.
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3. Other ideas from "Register-Sensitive Selection, Duplication, and
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Sequencing of Instructions".
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4. Scheduling for reduced register pressure. E.g. "Minimum Register
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Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
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and other related papers.
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http://citeseer.ist.psu.edu/govindarajan01minimum.html
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//===---------------------------------------------------------------------===//
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Should we promote i16 to i32 to avoid partial register update stalls?
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//===---------------------------------------------------------------------===//
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Leave any_extend as pseudo instruction and hint to register
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allocator. Delay codegen until post register allocation.
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//===---------------------------------------------------------------------===//
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Add a target specific hook to DAG combiner to handle SINT_TO_FP and
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FP_TO_SINT when the source operand is already in memory.
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//===---------------------------------------------------------------------===//
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Model X86 EFLAGS as a real register to avoid redudant cmp / test. e.g.
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cmpl $1, %eax
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setg %al
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testb %al, %al # unnecessary
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jne .BB7
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//===---------------------------------------------------------------------===//
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Count leading zeros and count trailing zeros:
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int clz(int X) { return __builtin_clz(X); }
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int ctz(int X) { return __builtin_ctz(X); }
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$ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
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clz:
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bsr %eax, DWORD PTR [%esp+4]
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xor %eax, 31
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ret
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ctz:
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bsf %eax, DWORD PTR [%esp+4]
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ret
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however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
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aren't.
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//===---------------------------------------------------------------------===//
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Use push/pop instructions in prolog/epilog sequences instead of stores off
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ESP (certain code size win, perf win on some [which?] processors).
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Also, it appears icc use push for parameter passing. Need to investigate.
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//===---------------------------------------------------------------------===//
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Only use inc/neg/not instructions on processors where they are faster than
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add/sub/xor. They are slower on the P4 due to only updating some processor
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flags.
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//===---------------------------------------------------------------------===//
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Open code rint,floor,ceil,trunc:
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http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02006.html
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http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02011.html
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//===---------------------------------------------------------------------===//
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Combine: a = sin(x), b = cos(x) into a,b = sincos(x).
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Expand these to calls of sin/cos and stores:
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double sincos(double x, double *sin, double *cos);
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float sincosf(float x, float *sin, float *cos);
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long double sincosl(long double x, long double *sin, long double *cos);
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Doing so could allow SROA of the destination pointers. See also:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17687
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//===---------------------------------------------------------------------===//
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The instruction selector sometimes misses folding a load into a compare. The
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pattern is written as (cmp reg, (load p)). Because the compare isn't
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commutative, it is not matched with the load on both sides. The dag combiner
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should be made smart enough to cannonicalize the load into the RHS of a compare
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when it can invert the result of the compare for free.
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//===---------------------------------------------------------------------===//
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LSR should be turned on for the X86 backend and tuned to take advantage of its
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addressing modes.
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//===---------------------------------------------------------------------===//
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When compiled with unsafemath enabled, "main" should enable SSE DAZ mode and
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other fast SSE modes.
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//===---------------------------------------------------------------------===//
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Think about doing i64 math in SSE regs.
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//===---------------------------------------------------------------------===//
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The DAG Isel doesn't fold the loads into the adds in this testcase. The
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pattern selector does. This is because the chain value of the load gets
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selected first, and the loads aren't checking to see if they are only used by
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and add.
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.ll:
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int %test(int* %x, int* %y, int* %z) {
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%X = load int* %x
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%Y = load int* %y
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%Z = load int* %z
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%a = add int %X, %Y
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%b = add int %a, %Z
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ret int %b
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}
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dag isel:
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_test:
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movl 4(%esp), %eax
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movl (%eax), %eax
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movl 8(%esp), %ecx
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movl (%ecx), %ecx
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addl %ecx, %eax
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movl 12(%esp), %ecx
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movl (%ecx), %ecx
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addl %ecx, %eax
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ret
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pattern isel:
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_test:
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movl 12(%esp), %ecx
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movl 4(%esp), %edx
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movl 8(%esp), %eax
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movl (%eax), %eax
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addl (%edx), %eax
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addl (%ecx), %eax
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ret
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This is bad for register pressure, though the dag isel is producing a
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better schedule. :)
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//===---------------------------------------------------------------------===//
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This testcase should have no SSE instructions in it, and only one load from
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a constant pool:
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double %test3(bool %B) {
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%C = select bool %B, double 123.412, double 523.01123123
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ret double %C
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}
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Currently, the select is being lowered, which prevents the dag combiner from
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turning 'select (load CPI1), (load CPI2)' -> 'load (select CPI1, CPI2)'
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The pattern isel got this one right.
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//===---------------------------------------------------------------------===//
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We need to lower switch statements to tablejumps when appropriate instead of
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always into binary branch trees.
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//===---------------------------------------------------------------------===//
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SSE doesn't have [mem] op= reg instructions. If we have an SSE instruction
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like this:
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X += y
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and the register allocator decides to spill X, it is cheaper to emit this as:
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Y += [xslot]
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store Y -> [xslot]
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than as:
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tmp = [xslot]
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tmp += y
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store tmp -> [xslot]
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..and this uses one fewer register (so this should be done at load folding
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time, not at spiller time). *Note* however that this can only be done
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if Y is dead. Here's a testcase:
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%.str_3 = external global [15 x sbyte] ; <[15 x sbyte]*> [#uses=0]
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implementation ; Functions:
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declare void %printf(int, ...)
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void %main() {
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build_tree.exit:
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br label %no_exit.i7
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no_exit.i7: ; preds = %no_exit.i7, %build_tree.exit
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%tmp.0.1.0.i9 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.34.i18, %no_exit.i7 ] ; <double> [#uses=1]
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%tmp.0.0.0.i10 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.28.i16, %no_exit.i7 ] ; <double> [#uses=1]
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%tmp.28.i16 = add double %tmp.0.0.0.i10, 0.000000e+00
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%tmp.34.i18 = add double %tmp.0.1.0.i9, 0.000000e+00
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br bool false, label %Compute_Tree.exit23, label %no_exit.i7
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Compute_Tree.exit23: ; preds = %no_exit.i7
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tail call void (int, ...)* %printf( int 0 )
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store double %tmp.34.i18, double* null
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ret void
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}
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We currently emit:
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.BBmain_1:
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xorpd %XMM1, %XMM1
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addsd %XMM0, %XMM1
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*** movsd %XMM2, QWORD PTR [%ESP + 8]
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*** addsd %XMM2, %XMM1
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*** movsd QWORD PTR [%ESP + 8], %XMM2
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jmp .BBmain_1 # no_exit.i7
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This is a bugpoint reduced testcase, which is why the testcase doesn't make
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much sense (e.g. its an infinite loop). :)
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//===---------------------------------------------------------------------===//
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None of the FPStack instructions are handled in
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X86RegisterInfo::foldMemoryOperand, which prevents the spiller from
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folding spill code into the instructions.
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//===---------------------------------------------------------------------===//
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In many cases, LLVM generates code like this:
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_test:
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movl 8(%esp), %eax
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cmpl %eax, 4(%esp)
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setl %al
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movzbl %al, %eax
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ret
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on some processors (which ones?), it is more efficient to do this:
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_test:
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movl 8(%esp), %ebx
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xor %eax, %eax
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cmpl %ebx, 4(%esp)
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setl %al
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ret
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Doing this correctly is tricky though, as the xor clobbers the flags.
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//===---------------------------------------------------------------------===//
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We should generate 'test' instead of 'cmp' in various cases, e.g.:
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bool %test(int %X) {
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%Y = shl int %X, ubyte 1
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%C = seteq int %Y, 0
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ret bool %C
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}
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bool %test(int %X) {
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%Y = and int %X, 8
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%C = seteq int %Y, 0
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ret bool %C
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}
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This may just be a matter of using 'test' to write bigger patterns for X86cmp.
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//===---------------------------------------------------------------------===//
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SSE should implement 'select_cc' using 'emulated conditional moves' that use
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pcmp/pand/pandn/por to do a selection instead of a conditional branch:
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double %X(double %Y, double %Z, double %A, double %B) {
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%C = setlt double %A, %B
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%z = add double %Z, 0.0 ;; select operand is not a load
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%D = select bool %C, double %Y, double %z
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ret double %D
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}
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We currently emit:
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_X:
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subl $12, %esp
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xorpd %xmm0, %xmm0
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addsd 24(%esp), %xmm0
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movsd 32(%esp), %xmm1
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movsd 16(%esp), %xmm2
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ucomisd 40(%esp), %xmm1
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jb LBB_X_2
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LBB_X_1:
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movsd %xmm0, %xmm2
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LBB_X_2:
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movsd %xmm2, (%esp)
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fldl (%esp)
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addl $12, %esp
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ret
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//===---------------------------------------------------------------------===//
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We should generate bts/btr/etc instructions on targets where they are cheap or
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when codesize is important. e.g., for:
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void setbit(int *target, int bit) {
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*target |= (1 << bit);
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}
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void clearbit(int *target, int bit) {
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*target &= ~(1 << bit);
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}
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//===---------------------------------------------------------------------===//
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Instead of the following for memset char*, 1, 10:
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movl $16843009, 4(%edx)
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movl $16843009, (%edx)
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movw $257, 8(%edx)
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It might be better to generate
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movl $16843009, %eax
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movl %eax, 4(%edx)
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movl %eax, (%edx)
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movw al, 8(%edx)
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when we can spare a register. It reduces code size.
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//===---------------------------------------------------------------------===//
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It's not clear whether we should use pxor or xorps / xorpd to clear XMM
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registers. The choice may depend on subtarget information. We should do some
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more experiments on different x86 machines.
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//===---------------------------------------------------------------------===//
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Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
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get this:
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int %test1(int %X) {
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%Y = div int %X, 8
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ret int %Y
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}
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_test1:
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movl 4(%esp), %eax
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movl %eax, %ecx
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sarl $31, %ecx
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shrl $29, %ecx
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addl %ecx, %eax
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sarl $3, %eax
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ret
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GCC knows several different ways to codegen it, one of which is this:
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_test1:
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movl 4(%esp), %eax
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cmpl $-1, %eax
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leal 7(%eax), %ecx
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cmovle %ecx, %eax
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sarl $3, %eax
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ret
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which is probably slower, but it's interesting at least :)
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//===---------------------------------------------------------------------===//
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Currently the x86 codegen isn't very good at mixing SSE and FPStack
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code:
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unsigned int foo(double x) { return x; }
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foo:
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subl $20, %esp
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movsd 24(%esp), %xmm0
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movsd %xmm0, 8(%esp)
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fldl 8(%esp)
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fisttpll (%esp)
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movl (%esp), %eax
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addl $20, %esp
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ret
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This will be solved when we go to a dynamic programming based isel.
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//===---------------------------------------------------------------------===//
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Make use of floating point min / max instructions. Perhaps introduce ISD::FMIN
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and ISD::FMAX node types?
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//===---------------------------------------------------------------------===//
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The first BB of this code:
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declare bool %foo()
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int %bar() {
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%V = call bool %foo()
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br bool %V, label %T, label %F
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T:
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ret int 1
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F:
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call bool %foo()
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ret int 12
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}
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compiles to:
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_bar:
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subl $12, %esp
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call L_foo$stub
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xorb $1, %al
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testb %al, %al
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jne LBB_bar_2 # F
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It would be better to emit "cmp %al, 1" than a xor and test.
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//===---------------------------------------------------------------------===//
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Enable X86InstrInfo::convertToThreeAddress().
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//===---------------------------------------------------------------------===//
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Investigate whether it is better to codegen the following
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%tmp.1 = mul int %x, 9
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to
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movl 4(%esp), %eax
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leal (%eax,%eax,8), %eax
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as opposed to what llc is currently generating:
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imull $9, 4(%esp), %eax
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Currently the load folding imull has a higher complexity than the LEA32 pattern.
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//===---------------------------------------------------------------------===//
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Lower memcpy / memset to a series of SSE 128 bit move instructions when it's
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feasible.
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//===---------------------------------------------------------------------===//
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Teach the coallescer to commute 2-addr instructions, allowing us to eliminate
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the reg-reg copy in this example:
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float foo(int *x, float *y, unsigned c) {
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float res = 0.0;
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unsigned i;
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for (i = 0; i < c; i++) {
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float xx = (float)x[i];
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xx = xx * y[i];
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xx += res;
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res = xx;
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}
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return res;
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}
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LBB_foo_3: # no_exit
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cvtsi2ss %XMM0, DWORD PTR [%EDX + 4*%ESI]
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mulss %XMM0, DWORD PTR [%EAX + 4*%ESI]
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addss %XMM0, %XMM1
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inc %ESI
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cmp %ESI, %ECX
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**** movaps %XMM1, %XMM0
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jb LBB_foo_3 # no_exit
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//===---------------------------------------------------------------------===//
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Codegen:
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if (copysign(1.0, x) == copysign(1.0, y))
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into:
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if (x^y & mask)
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when using SSE.
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|
//===---------------------------------------------------------------------===//
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Optimize this into something reasonable:
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x * copysign(1.0, y) * copysign(1.0, z)
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//===---------------------------------------------------------------------===//
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|
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Optimize copysign(x, *y) to use an integer load from y.
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|
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//===---------------------------------------------------------------------===//
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|