mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
6b7b725179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207505 91177308-0d34-0410-b5e6-96231b3b80d8
358 lines
12 KiB
C++
358 lines
12 KiB
C++
//===-- NVPTXReplaceImageHandles.cpp - Replace image handles for Fermi ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// On Fermi, image handles are not supported. To work around this, we traverse
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// the machine code and replace image handles with concrete symbols. For this
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// to work reliably, inlining of all function call must be performed.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTX.h"
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#include "NVPTXMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/DenseSet.h"
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using namespace llvm;
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namespace {
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class NVPTXReplaceImageHandles : public MachineFunctionPass {
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private:
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static char ID;
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DenseSet<MachineInstr *> InstrsToRemove;
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public:
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NVPTXReplaceImageHandles();
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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bool processInstr(MachineInstr &MI);
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void replaceImageHandle(MachineOperand &Op, MachineFunction &MF);
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};
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}
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char NVPTXReplaceImageHandles::ID = 0;
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NVPTXReplaceImageHandles::NVPTXReplaceImageHandles()
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: MachineFunctionPass(ID) {}
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bool NVPTXReplaceImageHandles::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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InstrsToRemove.clear();
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
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++BI) {
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for (MachineBasicBlock::iterator I = (*BI).begin(), E = (*BI).end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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Changed |= processInstr(MI);
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}
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}
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// Now clean up any handle-access instructions
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// This is needed in debug mode when code cleanup passes are not executed,
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// but we need the handle access to be eliminated because they are not
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// valid instructions when image handles are disabled.
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for (DenseSet<MachineInstr *>::iterator I = InstrsToRemove.begin(),
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E = InstrsToRemove.end(); I != E; ++I) {
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(*I)->eraseFromParent();
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}
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return Changed;
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}
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bool NVPTXReplaceImageHandles::processInstr(MachineInstr &MI) {
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MachineFunction &MF = *MI.getParent()->getParent();
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// Check if we have a surface/texture instruction
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switch (MI.getOpcode()) {
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default: return false;
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case NVPTX::TEX_1D_F32_I32:
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case NVPTX::TEX_1D_F32_F32:
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case NVPTX::TEX_1D_F32_F32_LEVEL:
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case NVPTX::TEX_1D_F32_F32_GRAD:
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case NVPTX::TEX_1D_I32_I32:
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case NVPTX::TEX_1D_I32_F32:
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case NVPTX::TEX_1D_I32_F32_LEVEL:
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case NVPTX::TEX_1D_I32_F32_GRAD:
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case NVPTX::TEX_1D_ARRAY_F32_I32:
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case NVPTX::TEX_1D_ARRAY_F32_F32:
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case NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL:
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case NVPTX::TEX_1D_ARRAY_F32_F32_GRAD:
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case NVPTX::TEX_1D_ARRAY_I32_I32:
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case NVPTX::TEX_1D_ARRAY_I32_F32:
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case NVPTX::TEX_1D_ARRAY_I32_F32_LEVEL:
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case NVPTX::TEX_1D_ARRAY_I32_F32_GRAD:
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case NVPTX::TEX_2D_F32_I32:
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case NVPTX::TEX_2D_F32_F32:
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case NVPTX::TEX_2D_F32_F32_LEVEL:
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case NVPTX::TEX_2D_F32_F32_GRAD:
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case NVPTX::TEX_2D_I32_I32:
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case NVPTX::TEX_2D_I32_F32:
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case NVPTX::TEX_2D_I32_F32_LEVEL:
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case NVPTX::TEX_2D_I32_F32_GRAD:
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case NVPTX::TEX_2D_ARRAY_F32_I32:
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case NVPTX::TEX_2D_ARRAY_F32_F32:
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case NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL:
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case NVPTX::TEX_2D_ARRAY_F32_F32_GRAD:
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case NVPTX::TEX_2D_ARRAY_I32_I32:
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case NVPTX::TEX_2D_ARRAY_I32_F32:
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case NVPTX::TEX_2D_ARRAY_I32_F32_LEVEL:
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case NVPTX::TEX_2D_ARRAY_I32_F32_GRAD:
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case NVPTX::TEX_3D_F32_I32:
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case NVPTX::TEX_3D_F32_F32:
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case NVPTX::TEX_3D_F32_F32_LEVEL:
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case NVPTX::TEX_3D_F32_F32_GRAD:
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case NVPTX::TEX_3D_I32_I32:
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case NVPTX::TEX_3D_I32_F32:
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case NVPTX::TEX_3D_I32_F32_LEVEL:
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case NVPTX::TEX_3D_I32_F32_GRAD: {
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// This is a texture fetch, so operand 4 is a texref and operand 5 is
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// a samplerref
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MachineOperand &TexHandle = MI.getOperand(4);
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MachineOperand &SampHandle = MI.getOperand(5);
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replaceImageHandle(TexHandle, MF);
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replaceImageHandle(SampHandle, MF);
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return true;
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}
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case NVPTX::SULD_1D_I8_TRAP:
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case NVPTX::SULD_1D_I16_TRAP:
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case NVPTX::SULD_1D_I32_TRAP:
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case NVPTX::SULD_1D_ARRAY_I8_TRAP:
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case NVPTX::SULD_1D_ARRAY_I16_TRAP:
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case NVPTX::SULD_1D_ARRAY_I32_TRAP:
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case NVPTX::SULD_2D_I8_TRAP:
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case NVPTX::SULD_2D_I16_TRAP:
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case NVPTX::SULD_2D_I32_TRAP:
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case NVPTX::SULD_2D_ARRAY_I8_TRAP:
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case NVPTX::SULD_2D_ARRAY_I16_TRAP:
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case NVPTX::SULD_2D_ARRAY_I32_TRAP:
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case NVPTX::SULD_3D_I8_TRAP:
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case NVPTX::SULD_3D_I16_TRAP:
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case NVPTX::SULD_3D_I32_TRAP: {
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// This is a V1 surface load, so operand 1 is a surfref
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MachineOperand &SurfHandle = MI.getOperand(1);
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replaceImageHandle(SurfHandle, MF);
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return true;
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}
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case NVPTX::SULD_1D_V2I8_TRAP:
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case NVPTX::SULD_1D_V2I16_TRAP:
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case NVPTX::SULD_1D_V2I32_TRAP:
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case NVPTX::SULD_1D_ARRAY_V2I8_TRAP:
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case NVPTX::SULD_1D_ARRAY_V2I16_TRAP:
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case NVPTX::SULD_1D_ARRAY_V2I32_TRAP:
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case NVPTX::SULD_2D_V2I8_TRAP:
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case NVPTX::SULD_2D_V2I16_TRAP:
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case NVPTX::SULD_2D_V2I32_TRAP:
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case NVPTX::SULD_2D_ARRAY_V2I8_TRAP:
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case NVPTX::SULD_2D_ARRAY_V2I16_TRAP:
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case NVPTX::SULD_2D_ARRAY_V2I32_TRAP:
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case NVPTX::SULD_3D_V2I8_TRAP:
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case NVPTX::SULD_3D_V2I16_TRAP:
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case NVPTX::SULD_3D_V2I32_TRAP: {
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// This is a V2 surface load, so operand 2 is a surfref
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MachineOperand &SurfHandle = MI.getOperand(2);
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replaceImageHandle(SurfHandle, MF);
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return true;
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}
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case NVPTX::SULD_1D_V4I8_TRAP:
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case NVPTX::SULD_1D_V4I16_TRAP:
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case NVPTX::SULD_1D_V4I32_TRAP:
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case NVPTX::SULD_1D_ARRAY_V4I8_TRAP:
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case NVPTX::SULD_1D_ARRAY_V4I16_TRAP:
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case NVPTX::SULD_1D_ARRAY_V4I32_TRAP:
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case NVPTX::SULD_2D_V4I8_TRAP:
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case NVPTX::SULD_2D_V4I16_TRAP:
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case NVPTX::SULD_2D_V4I32_TRAP:
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case NVPTX::SULD_2D_ARRAY_V4I8_TRAP:
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case NVPTX::SULD_2D_ARRAY_V4I16_TRAP:
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case NVPTX::SULD_2D_ARRAY_V4I32_TRAP:
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case NVPTX::SULD_3D_V4I8_TRAP:
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case NVPTX::SULD_3D_V4I16_TRAP:
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case NVPTX::SULD_3D_V4I32_TRAP: {
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// This is a V4 surface load, so operand 4 is a surfref
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MachineOperand &SurfHandle = MI.getOperand(4);
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replaceImageHandle(SurfHandle, MF);
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return true;
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}
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case NVPTX::SUST_B_1D_B8_TRAP:
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case NVPTX::SUST_B_1D_B16_TRAP:
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case NVPTX::SUST_B_1D_B32_TRAP:
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case NVPTX::SUST_B_1D_V2B8_TRAP:
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case NVPTX::SUST_B_1D_V2B16_TRAP:
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case NVPTX::SUST_B_1D_V2B32_TRAP:
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case NVPTX::SUST_B_1D_V4B8_TRAP:
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case NVPTX::SUST_B_1D_V4B16_TRAP:
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case NVPTX::SUST_B_1D_V4B32_TRAP:
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case NVPTX::SUST_B_1D_ARRAY_B8_TRAP:
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case NVPTX::SUST_B_1D_ARRAY_B16_TRAP:
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case NVPTX::SUST_B_1D_ARRAY_B32_TRAP:
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case NVPTX::SUST_B_1D_ARRAY_V2B8_TRAP:
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case NVPTX::SUST_B_1D_ARRAY_V2B16_TRAP:
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case NVPTX::SUST_B_1D_ARRAY_V2B32_TRAP:
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case NVPTX::SUST_B_1D_ARRAY_V4B8_TRAP:
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case NVPTX::SUST_B_1D_ARRAY_V4B16_TRAP:
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case NVPTX::SUST_B_1D_ARRAY_V4B32_TRAP:
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case NVPTX::SUST_B_2D_B8_TRAP:
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case NVPTX::SUST_B_2D_B16_TRAP:
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case NVPTX::SUST_B_2D_B32_TRAP:
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case NVPTX::SUST_B_2D_V2B8_TRAP:
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case NVPTX::SUST_B_2D_V2B16_TRAP:
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case NVPTX::SUST_B_2D_V2B32_TRAP:
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case NVPTX::SUST_B_2D_V4B8_TRAP:
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case NVPTX::SUST_B_2D_V4B16_TRAP:
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case NVPTX::SUST_B_2D_V4B32_TRAP:
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case NVPTX::SUST_B_2D_ARRAY_B8_TRAP:
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case NVPTX::SUST_B_2D_ARRAY_B16_TRAP:
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case NVPTX::SUST_B_2D_ARRAY_B32_TRAP:
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case NVPTX::SUST_B_2D_ARRAY_V2B8_TRAP:
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case NVPTX::SUST_B_2D_ARRAY_V2B16_TRAP:
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case NVPTX::SUST_B_2D_ARRAY_V2B32_TRAP:
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case NVPTX::SUST_B_2D_ARRAY_V4B8_TRAP:
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case NVPTX::SUST_B_2D_ARRAY_V4B16_TRAP:
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case NVPTX::SUST_B_2D_ARRAY_V4B32_TRAP:
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case NVPTX::SUST_B_3D_B8_TRAP:
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case NVPTX::SUST_B_3D_B16_TRAP:
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case NVPTX::SUST_B_3D_B32_TRAP:
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case NVPTX::SUST_B_3D_V2B8_TRAP:
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case NVPTX::SUST_B_3D_V2B16_TRAP:
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case NVPTX::SUST_B_3D_V2B32_TRAP:
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case NVPTX::SUST_B_3D_V4B8_TRAP:
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case NVPTX::SUST_B_3D_V4B16_TRAP:
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case NVPTX::SUST_B_3D_V4B32_TRAP:
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case NVPTX::SUST_P_1D_B8_TRAP:
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case NVPTX::SUST_P_1D_B16_TRAP:
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case NVPTX::SUST_P_1D_B32_TRAP:
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case NVPTX::SUST_P_1D_V2B8_TRAP:
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case NVPTX::SUST_P_1D_V2B16_TRAP:
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case NVPTX::SUST_P_1D_V2B32_TRAP:
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case NVPTX::SUST_P_1D_V4B8_TRAP:
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case NVPTX::SUST_P_1D_V4B16_TRAP:
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case NVPTX::SUST_P_1D_V4B32_TRAP:
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case NVPTX::SUST_P_1D_ARRAY_B8_TRAP:
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case NVPTX::SUST_P_1D_ARRAY_B16_TRAP:
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case NVPTX::SUST_P_1D_ARRAY_B32_TRAP:
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case NVPTX::SUST_P_1D_ARRAY_V2B8_TRAP:
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case NVPTX::SUST_P_1D_ARRAY_V2B16_TRAP:
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case NVPTX::SUST_P_1D_ARRAY_V2B32_TRAP:
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case NVPTX::SUST_P_1D_ARRAY_V4B8_TRAP:
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case NVPTX::SUST_P_1D_ARRAY_V4B16_TRAP:
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case NVPTX::SUST_P_1D_ARRAY_V4B32_TRAP:
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case NVPTX::SUST_P_2D_B8_TRAP:
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case NVPTX::SUST_P_2D_B16_TRAP:
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case NVPTX::SUST_P_2D_B32_TRAP:
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case NVPTX::SUST_P_2D_V2B8_TRAP:
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case NVPTX::SUST_P_2D_V2B16_TRAP:
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case NVPTX::SUST_P_2D_V2B32_TRAP:
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case NVPTX::SUST_P_2D_V4B8_TRAP:
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case NVPTX::SUST_P_2D_V4B16_TRAP:
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case NVPTX::SUST_P_2D_V4B32_TRAP:
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case NVPTX::SUST_P_2D_ARRAY_B8_TRAP:
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case NVPTX::SUST_P_2D_ARRAY_B16_TRAP:
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case NVPTX::SUST_P_2D_ARRAY_B32_TRAP:
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case NVPTX::SUST_P_2D_ARRAY_V2B8_TRAP:
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case NVPTX::SUST_P_2D_ARRAY_V2B16_TRAP:
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case NVPTX::SUST_P_2D_ARRAY_V2B32_TRAP:
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case NVPTX::SUST_P_2D_ARRAY_V4B8_TRAP:
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case NVPTX::SUST_P_2D_ARRAY_V4B16_TRAP:
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case NVPTX::SUST_P_2D_ARRAY_V4B32_TRAP:
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case NVPTX::SUST_P_3D_B8_TRAP:
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case NVPTX::SUST_P_3D_B16_TRAP:
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case NVPTX::SUST_P_3D_B32_TRAP:
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case NVPTX::SUST_P_3D_V2B8_TRAP:
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case NVPTX::SUST_P_3D_V2B16_TRAP:
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case NVPTX::SUST_P_3D_V2B32_TRAP:
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case NVPTX::SUST_P_3D_V4B8_TRAP:
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case NVPTX::SUST_P_3D_V4B16_TRAP:
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case NVPTX::SUST_P_3D_V4B32_TRAP: {
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// This is a surface store, so operand 0 is a surfref
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MachineOperand &SurfHandle = MI.getOperand(0);
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replaceImageHandle(SurfHandle, MF);
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return true;
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}
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case NVPTX::TXQ_CHANNEL_ORDER:
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case NVPTX::TXQ_CHANNEL_DATA_TYPE:
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case NVPTX::TXQ_WIDTH:
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case NVPTX::TXQ_HEIGHT:
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case NVPTX::TXQ_DEPTH:
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case NVPTX::TXQ_ARRAY_SIZE:
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case NVPTX::TXQ_NUM_SAMPLES:
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case NVPTX::TXQ_NUM_MIPMAP_LEVELS:
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case NVPTX::SUQ_CHANNEL_ORDER:
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case NVPTX::SUQ_CHANNEL_DATA_TYPE:
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case NVPTX::SUQ_WIDTH:
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case NVPTX::SUQ_HEIGHT:
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case NVPTX::SUQ_DEPTH:
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case NVPTX::SUQ_ARRAY_SIZE: {
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// This is a query, so operand 1 is a surfref/texref
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MachineOperand &Handle = MI.getOperand(1);
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replaceImageHandle(Handle, MF);
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return true;
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}
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}
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}
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void NVPTXReplaceImageHandles::
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replaceImageHandle(MachineOperand &Op, MachineFunction &MF) {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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NVPTXMachineFunctionInfo *MFI = MF.getInfo<NVPTXMachineFunctionInfo>();
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// Which instruction defines the handle?
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MachineInstr *MI = MRI.getVRegDef(Op.getReg());
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assert(MI && "No def for image handle vreg?");
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MachineInstr &TexHandleDef = *MI;
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switch (TexHandleDef.getOpcode()) {
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case NVPTX::LD_i64_avar: {
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// The handle is a parameter value being loaded, replace with the
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// parameter symbol
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assert(TexHandleDef.getOperand(6).isSymbol() && "Load is not a symbol!");
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StringRef Sym = TexHandleDef.getOperand(6).getSymbolName();
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std::string ParamBaseName = MF.getName();
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ParamBaseName += "_param_";
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assert(Sym.startswith(ParamBaseName) && "Invalid symbol reference");
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unsigned Param = atoi(Sym.data()+ParamBaseName.size());
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std::string NewSym;
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raw_string_ostream NewSymStr(NewSym);
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NewSymStr << MF.getFunction()->getName() << "_param_" << Param;
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Op.ChangeToImmediate(
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MFI->getImageHandleSymbolIndex(NewSymStr.str().c_str()));
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InstrsToRemove.insert(&TexHandleDef);
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break;
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}
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case NVPTX::texsurf_handles: {
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// The handle is a global variable, replace with the global variable name
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assert(TexHandleDef.getOperand(1).isGlobal() && "Load is not a global!");
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const GlobalValue *GV = TexHandleDef.getOperand(1).getGlobal();
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assert(GV->hasName() && "Global sampler must be named!");
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Op.ChangeToImmediate(MFI->getImageHandleSymbolIndex(GV->getName().data()));
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InstrsToRemove.insert(&TexHandleDef);
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break;
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}
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default:
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llvm_unreachable("Unknown instruction operating on handle");
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}
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}
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MachineFunctionPass *llvm::createNVPTXReplaceImageHandlesPass() {
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return new NVPTXReplaceImageHandles();
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}
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