mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-05 01:30:18 +00:00
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
160 lines
5.7 KiB
C++
160 lines
5.7 KiB
C++
//=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the custom routines for the ARM Calling Convention that
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// aren't done by tablegen.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMCALLINGCONV_H
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#define ARMCALLINGCONV_H
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/Target/TargetInstrInfo.h"
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namespace llvm {
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// APCS f64 is in register pairs, possibly split to stack
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static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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CCState &State, bool CanFail) {
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static const uint16_t RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
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// Try to get the first register.
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if (unsigned Reg = State.AllocateReg(RegList, 4))
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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else {
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// For the 2nd half of a v2f64, do not fail.
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if (CanFail)
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return false;
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// Put the whole thing on the stack.
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State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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State.AllocateStack(8, 4),
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LocVT, LocInfo));
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return true;
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}
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// Try to get the second register.
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if (unsigned Reg = State.AllocateReg(RegList, 4))
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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else
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State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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State.AllocateStack(4, 4),
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LocVT, LocInfo));
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return true;
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}
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static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
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return false;
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if (LocVT == MVT::v2f64 &&
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!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
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return false;
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return true; // we handled it
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}
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// AAPCS f64 is in aligned register pairs
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static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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CCState &State, bool CanFail) {
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static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 };
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static const uint16_t LoRegList[] = { ARM::R1, ARM::R3 };
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static const uint16_t ShadowRegList[] = { ARM::R0, ARM::R1 };
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unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
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if (Reg == 0) {
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// For the 2nd half of a v2f64, do not just fail.
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if (CanFail)
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return false;
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// Put the whole thing on the stack.
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State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
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State.AllocateStack(8, 8),
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LocVT, LocInfo));
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return true;
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}
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unsigned i;
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for (i = 0; i < 2; ++i)
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if (HiRegList[i] == Reg)
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break;
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unsigned T = State.AllocateReg(LoRegList[i]);
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(void)T;
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assert(T == LoRegList[i] && "Could not allocate register");
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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LocVT, LocInfo));
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return true;
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}
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static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
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return false;
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if (LocVT == MVT::v2f64 &&
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!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
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return false;
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return true; // we handled it
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}
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static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo, CCState &State) {
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static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 };
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static const uint16_t LoRegList[] = { ARM::R1, ARM::R3 };
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unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
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if (Reg == 0)
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return false; // we didn't handle it
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unsigned i;
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for (i = 0; i < 2; ++i)
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if (HiRegList[i] == Reg)
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break;
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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LocVT, LocInfo));
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return true;
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}
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static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
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return false;
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if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
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return false;
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return true; // we handled it
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}
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static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
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State);
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}
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} // End llvm namespace
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#endif
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