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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170349 91177308-0d34-0410-b5e6-96231b3b80d8
404 lines
9.2 KiB
C++
404 lines
9.2 KiB
C++
//===- MachOFormat.h - Mach-O Format Structures And Constants ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares various structures and constants which are platform
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// independent and can be shared by any client which wishes to interact with
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// Mach object files.
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//
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// The definitions here are purposely chosen to match the LLVM style as opposed
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// to following the platform specific definition of the format.
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//
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// On a Mach system, see the <mach-o/...> includes for more information, in
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// particular <mach-o/loader.h>.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_OBJECT_MACHOFORMAT_H
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#define LLVM_OBJECT_MACHOFORMAT_H
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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namespace object {
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/// General Mach platform information.
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namespace mach {
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/// @name CPU Type and Subtype Information
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/// {
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/// \brief Capability bits used in CPU type encoding.
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enum CPUTypeFlagsMask {
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CTFM_ArchMask = 0xFF000000,
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CTFM_ArchABI64 = 0x01000000
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};
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/// \brief Machine type IDs used in CPU type encoding.
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enum CPUTypeMachine {
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CTM_i386 = 7,
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CTM_x86_64 = CTM_i386 | CTFM_ArchABI64,
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CTM_ARM = 12,
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CTM_SPARC = 14,
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CTM_PowerPC = 18,
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CTM_PowerPC64 = CTM_PowerPC | CTFM_ArchABI64
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};
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/// \brief Capability bits used in CPU subtype encoding.
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enum CPUSubtypeFlagsMask {
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CSFM_SubtypeMask = 0xFF000000,
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CSFM_SubtypeLib64 = 0x80000000
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};
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/// \brief ARM Machine Subtypes.
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enum CPUSubtypeARM {
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CSARM_ALL = 0,
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CSARM_V4T = 5,
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CSARM_V6 = 6,
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CSARM_V5TEJ = 7,
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CSARM_XSCALE = 8,
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CSARM_V7 = 9,
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CSARM_V7F = 10,
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CSARM_V7S = 11,
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CSARM_V7K = 12
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};
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/// \brief PowerPC Machine Subtypes.
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enum CPUSubtypePowerPC {
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CSPPC_ALL = 0
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};
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/// \brief SPARC Machine Subtypes.
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enum CPUSubtypeSPARC {
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CSSPARC_ALL = 0
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};
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/// \brief x86 Machine Subtypes.
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enum CPUSubtypeX86 {
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CSX86_ALL = 3
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};
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/// @}
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} // end namespace mach
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/// Format information for Mach object files.
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namespace macho {
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/// \brief Constants for structure sizes.
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enum StructureSizes {
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Header32Size = 28,
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Header64Size = 32,
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SegmentLoadCommand32Size = 56,
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SegmentLoadCommand64Size = 72,
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Section32Size = 68,
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Section64Size = 80,
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SymtabLoadCommandSize = 24,
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DysymtabLoadCommandSize = 80,
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Nlist32Size = 12,
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Nlist64Size = 16,
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RelocationInfoSize = 8,
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LinkeditLoadCommandSize = 16
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};
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/// \brief Constants for header magic field.
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enum HeaderMagic {
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HM_Object32 = 0xFEEDFACE, ///< 32-bit mach object file
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HM_Object64 = 0xFEEDFACF, ///< 64-bit mach object file
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HM_Universal = 0xCAFEBABE ///< Universal object file
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};
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/// \brief Header common to all Mach object files.
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struct Header {
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uint32_t Magic;
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uint32_t CPUType;
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uint32_t CPUSubtype;
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uint32_t FileType;
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uint32_t NumLoadCommands;
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uint32_t SizeOfLoadCommands;
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uint32_t Flags;
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};
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/// \brief Extended header for 64-bit object files.
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struct Header64Ext {
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uint32_t Reserved;
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};
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// See <mach-o/loader.h>.
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enum HeaderFileType {
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HFT_Object = 0x1
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};
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enum HeaderFlags {
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HF_SubsectionsViaSymbols = 0x2000
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};
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enum LoadCommandType {
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LCT_Segment = 0x1,
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LCT_Symtab = 0x2,
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LCT_Dysymtab = 0xb,
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LCT_Segment64 = 0x19,
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LCT_UUID = 0x1b,
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LCT_CodeSignature = 0x1d,
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LCT_SegmentSplitInfo = 0x1e,
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LCT_FunctionStarts = 0x26,
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LCT_DataInCode = 0x29
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};
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/// \brief Load command structure.
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struct LoadCommand {
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uint32_t Type;
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uint32_t Size;
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};
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/// @name Load Command Structures
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/// @{
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struct SegmentLoadCommand {
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uint32_t Type;
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uint32_t Size;
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char Name[16];
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uint32_t VMAddress;
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uint32_t VMSize;
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uint32_t FileOffset;
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uint32_t FileSize;
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uint32_t MaxVMProtection;
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uint32_t InitialVMProtection;
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uint32_t NumSections;
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uint32_t Flags;
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};
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struct Segment64LoadCommand {
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uint32_t Type;
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uint32_t Size;
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char Name[16];
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uint64_t VMAddress;
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uint64_t VMSize;
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uint64_t FileOffset;
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uint64_t FileSize;
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uint32_t MaxVMProtection;
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uint32_t InitialVMProtection;
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uint32_t NumSections;
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uint32_t Flags;
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};
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struct SymtabLoadCommand {
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uint32_t Type;
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uint32_t Size;
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uint32_t SymbolTableOffset;
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uint32_t NumSymbolTableEntries;
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uint32_t StringTableOffset;
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uint32_t StringTableSize;
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};
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struct DysymtabLoadCommand {
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uint32_t Type;
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uint32_t Size;
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uint32_t LocalSymbolsIndex;
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uint32_t NumLocalSymbols;
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uint32_t ExternalSymbolsIndex;
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uint32_t NumExternalSymbols;
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uint32_t UndefinedSymbolsIndex;
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uint32_t NumUndefinedSymbols;
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uint32_t TOCOffset;
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uint32_t NumTOCEntries;
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uint32_t ModuleTableOffset;
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uint32_t NumModuleTableEntries;
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uint32_t ReferenceSymbolTableOffset;
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uint32_t NumReferencedSymbolTableEntries;
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uint32_t IndirectSymbolTableOffset;
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uint32_t NumIndirectSymbolTableEntries;
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uint32_t ExternalRelocationTableOffset;
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uint32_t NumExternalRelocationTableEntries;
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uint32_t LocalRelocationTableOffset;
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uint32_t NumLocalRelocationTableEntries;
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};
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struct LinkeditDataLoadCommand {
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uint32_t Type;
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uint32_t Size;
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uint32_t DataOffset;
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uint32_t DataSize;
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};
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/// @}
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/// @name Section Data
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/// @{
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enum SectionFlags {
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SF_PureInstructions = 0x80000000
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};
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struct Section {
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char Name[16];
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char SegmentName[16];
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uint32_t Address;
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uint32_t Size;
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uint32_t Offset;
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uint32_t Align;
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uint32_t RelocationTableOffset;
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uint32_t NumRelocationTableEntries;
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uint32_t Flags;
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uint32_t Reserved1;
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uint32_t Reserved2;
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};
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struct Section64 {
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char Name[16];
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char SegmentName[16];
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uint64_t Address;
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uint64_t Size;
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uint32_t Offset;
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uint32_t Align;
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uint32_t RelocationTableOffset;
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uint32_t NumRelocationTableEntries;
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uint32_t Flags;
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uint32_t Reserved1;
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uint32_t Reserved2;
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uint32_t Reserved3;
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};
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/// @}
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/// @name Symbol Table Entries
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/// @{
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struct SymbolTableEntry {
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uint32_t StringIndex;
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uint8_t Type;
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uint8_t SectionIndex;
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uint16_t Flags;
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uint32_t Value;
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};
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// Despite containing a uint64_t, this structure is only 4-byte aligned within
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// a MachO file.
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#pragma pack(push)
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#pragma pack(4)
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struct Symbol64TableEntry {
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uint32_t StringIndex;
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uint8_t Type;
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uint8_t SectionIndex;
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uint16_t Flags;
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uint64_t Value;
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};
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#pragma pack(pop)
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/// @}
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/// @name Data-in-code Table Entry
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/// @{
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// See <mach-o/loader.h>.
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enum DataRegionType { Data = 1, JumpTable8, JumpTable16, JumpTable32 };
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struct DataInCodeTableEntry {
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uint32_t Offset; /* from mach_header to start of data region */
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uint16_t Length; /* number of bytes in data region */
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uint16_t Kind; /* a DataRegionType value */
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};
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/// @}
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/// @name Indirect Symbol Table
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/// @{
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struct IndirectSymbolTableEntry {
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uint32_t Index;
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};
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/// @}
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/// @name Relocation Data
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/// @{
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struct RelocationEntry {
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uint32_t Word0;
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uint32_t Word1;
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};
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/// @}
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// See <mach-o/nlist.h>.
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enum SymbolTypeType {
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STT_Undefined = 0x00,
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STT_Absolute = 0x02,
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STT_Section = 0x0e
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};
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enum SymbolTypeFlags {
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// If any of these bits are set, then the entry is a stab entry number (see
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// <mach-o/stab.h>. Otherwise the other masks apply.
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STF_StabsEntryMask = 0xe0,
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STF_TypeMask = 0x0e,
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STF_External = 0x01,
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STF_PrivateExtern = 0x10
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};
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/// IndirectSymbolFlags - Flags for encoding special values in the indirect
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/// symbol entry.
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enum IndirectSymbolFlags {
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ISF_Local = 0x80000000,
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ISF_Absolute = 0x40000000
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};
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/// RelocationFlags - Special flags for addresses.
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enum RelocationFlags {
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RF_Scattered = 0x80000000
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};
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/// Common relocation info types.
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enum RelocationInfoType {
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RIT_Vanilla = 0,
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RIT_Pair = 1,
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RIT_Difference = 2
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};
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/// Generic relocation info types, which are shared by some (but not all)
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/// platforms.
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enum RelocationInfoType_Generic {
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RIT_Generic_PreboundLazyPointer = 3,
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RIT_Generic_LocalDifference = 4,
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RIT_Generic_TLV = 5
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};
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/// X86_64 uses its own relocation types.
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enum RelocationInfoTypeX86_64 {
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// Note that x86_64 doesn't even share the common relocation types.
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RIT_X86_64_Unsigned = 0,
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RIT_X86_64_Signed = 1,
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RIT_X86_64_Branch = 2,
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RIT_X86_64_GOTLoad = 3,
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RIT_X86_64_GOT = 4,
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RIT_X86_64_Subtractor = 5,
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RIT_X86_64_Signed1 = 6,
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RIT_X86_64_Signed2 = 7,
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RIT_X86_64_Signed4 = 8,
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RIT_X86_64_TLV = 9
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};
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/// ARM uses its own relocation types.
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enum RelocationInfoTypeARM {
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RIT_ARM_LocalDifference = 3,
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RIT_ARM_PreboundLazyPointer = 4,
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RIT_ARM_Branch24Bit = 5,
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RIT_ARM_ThumbBranch22Bit = 6,
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RIT_ARM_ThumbBranch32Bit = 7,
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RIT_ARM_Half = 8,
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RIT_ARM_HalfDifference = 9
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};
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} // end namespace macho
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} // end namespace object
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} // end namespace llvm
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#endif
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