Chris Lattner 736a6ea3a2 Change the scheduler from adding nodes in allnodes order ... to adding them in a determinstic order (bottom up from the root) based on the structure of the graph itself. This updates tests for some random changes, interesting bits: CodeGen/Blackfin/promote-logic.ll no longer crashes. I have no idea why, but that's good right? CodeGen/X86/2009-07-16-LoadFoldingBug.ll also fails, but now compiles to have one fewer constant pool entry, making the expected load that was being folded disappear. Since it is an unreduced mass of gnast, I just removed it. This fixes PR6370 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97023 91177308-0d34-0410-b5e6-96231b3b80d8		2010-02-24 06:11:37 +00:00
..
2009-08-04-LowerExtract-Live.ll
2009-08-11-RegScavenger-CSR.ll
2009-08-15-LiveIn-SubReg.ll
2009-08-15-MissingDead.ll
2009-08-15-SetCC-Undef.ll	Teach dag combine to fold the following transformation more aggressively:	2010-01-06 19:38:29 +00:00
add-overflow.ll
add.ll
addsub-i128.ll
basic-i1.ll
basic-i8.ll
basic-i16.ll
basic-i32.ll
basic-i64.ll
basictest.ll
burg.ll
cmp64.ll
cmp-small-imm.ll
ct32.ll	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
ct64.ll	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
ctlz16.ll	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
ctlz64.ll
ctpop16.ll	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
cttz16.ll	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
cycles.ll
dg.exp
double-cast.ll
frameindex.ll
i1mem.ll
i1ops.ll
i8mem.ll
i17mem.ll
i56param.ll
i216mem.ll
i248mem.ll
i256mem.ll
i256param.ll
inline-asm.ll
int-setcc.ll
invalid-apint.ll
jumptable.ll
large-switch.ll
load-i16.ll
logic-i16.ll
many-args.ll
mulhu.ll
printf2.ll
printf.ll
promote-logic.ll	Change the scheduler from adding nodes in allnodes order	2010-02-24 06:11:37 +00:00
promote-setcc.ll
sdiv.ll
simple-select.ll
switch2.ll
switch.ll
sync-intr.ll