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27c28cef11
This is a medium term workaround until we have a more robust solution in the form of a register liveness utility for postRA passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166001 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.6 KiB
LLVM
54 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core2 -x86-early-ifcvt -enable-misched \
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; RUN: -misched=shuffle -misched-bottomup -verify-machineinstrs \
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; RUN: | FileCheck %s
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; REQUIRES: asserts
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;
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; Interesting MachineScheduler cases.
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;
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; FIXME: There should be an assert in the coalescer that we're not rematting
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; "not-quite-dead" copies, but that breaks a lot of tests <rdar://problem/11148682>.
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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; From oggenc.
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; After coalescing, we have a dead superreg (RAX) definition.
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;
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; CHECK: xorl %esi, %esi
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; CHECK: movl $32, %ecx
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; CHECK: rep;movsl
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define fastcc void @_preextrapolate_helper() nounwind uwtable ssp {
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entry:
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br i1 undef, label %for.cond.preheader, label %if.end
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for.cond.preheader: ; preds = %entry
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* null, i64 128, i32 4, i1 false) nounwind
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unreachable
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if.end: ; preds = %entry
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ret void
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}
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; The machine verifier checks that EFLAGS kill flags are updated when
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; the scheduler reorders cmovel instructions.
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;
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; CHECK: test
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; CHECK: cmovel
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; CHECK: cmovel
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; CHECK: call
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define void @foo(i32 %b) nounwind uwtable ssp {
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entry:
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%tobool = icmp ne i32 %b, 0
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br i1 %tobool, label %if.then, label %if.end
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if.then: ; preds = %entry
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br label %if.end
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if.end: ; preds = %if.then, %entry
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%v1 = phi i32 [1, %entry], [2, %if.then]
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%v2 = phi i32 [3, %entry], [4, %if.then]
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call void @bar(i32 %v1, i32 %v2)
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ret void
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}
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declare void @bar(i32,i32)
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