Michael Liao 13d08bf415 Fix an issue of pseudo atomic instruction DAG schedule ... - Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8		2013-01-22 21:47:38 +00:00
..
ARM	Remove some register allocation order dependencies.	2013-01-19 00:03:32 +00:00
CPP
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon	Add indexed load/store instructions for offset validation check.	2013-01-17 18:42:37 +00:00
MBlaze
Mips	[mips] Implement MipsRegisterInfo::getRegPressureLimit.	2013-01-22 21:34:25 +00:00
MSP430
NVPTX	[NVPTX] Fix crash with unnamed struct arguments	2012-12-05 20:50:28 +00:00
PowerPC	Restore reverted test case, this time with REQUIRES: asserts	2013-01-17 19:46:51 +00:00
R600	DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes	2013-01-02 22:13:01 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC
Thumb
Thumb2	Remove some register allocation order dependencies.	2013-01-19 00:03:32 +00:00
X86	Fix an issue of pseudo atomic instruction DAG schedule	2013-01-22 21:47:38 +00:00
XCore