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the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
1359 lines
48 KiB
C++
1359 lines
48 KiB
C++
//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format ARM assembly language.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "ARM.h"
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#include "ARMBuildAttrs.h"
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#include "ARMAddressingModes.h"
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#include "ARMConstantPoolValue.h"
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#include "InstPrinter/ARMInstPrinter.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMMCInstLower.h"
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#include "ARMTargetMachine.h"
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#include "ARMTargetObjectFile.h"
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#include "llvm/Analysis/DebugInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Module.h"
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#include "llvm/Type.h"
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#include "llvm/Assembly/Writer.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCObjectStreamer.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Target/Mangler.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cctype>
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using namespace llvm;
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namespace llvm {
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namespace ARM {
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enum DW_ISA {
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DW_ISA_ARM_thumb = 1,
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DW_ISA_ARM_arm = 2
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};
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}
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}
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namespace {
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// Per section and per symbol attributes are not supported.
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// To implement them we would need the ability to delay this emission
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// until the assembly file is fully parsed/generated as only then do we
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// know the symbol and section numbers.
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class AttributeEmitter {
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public:
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virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
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virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
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virtual void Finish() = 0;
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virtual ~AttributeEmitter() {}
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};
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class AsmAttributeEmitter : public AttributeEmitter {
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MCStreamer &Streamer;
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public:
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AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
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void MaybeSwitchVendor(StringRef Vendor) { }
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void EmitAttribute(unsigned Attribute, unsigned Value) {
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Streamer.EmitRawText("\t.eabi_attribute " +
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Twine(Attribute) + ", " + Twine(Value));
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}
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void Finish() { }
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};
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class ObjectAttributeEmitter : public AttributeEmitter {
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MCObjectStreamer &Streamer;
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StringRef CurrentVendor;
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SmallString<64> Contents;
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public:
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ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
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Streamer(Streamer_), CurrentVendor("") { }
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void MaybeSwitchVendor(StringRef Vendor) {
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assert(!Vendor.empty() && "Vendor cannot be empty.");
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if (CurrentVendor.empty())
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CurrentVendor = Vendor;
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else if (CurrentVendor == Vendor)
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return;
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else
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Finish();
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CurrentVendor = Vendor;
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assert(Contents.size() == 0);
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}
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void EmitAttribute(unsigned Attribute, unsigned Value) {
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// FIXME: should be ULEB
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Contents += Attribute;
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Contents += Value;
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}
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void Finish() {
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const size_t ContentsSize = Contents.size();
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// Vendor size + Vendor name + '\0'
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const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
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// Tag + Tag Size
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const size_t TagHeaderSize = 1 + 4;
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Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
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Streamer.EmitBytes(CurrentVendor, 0);
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Streamer.EmitIntValue(0, 1); // '\0'
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Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
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Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
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Streamer.EmitBytes(Contents, 0);
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Contents.clear();
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}
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};
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class ARMAsmPrinter : public AsmPrinter {
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when printing asm code for different targets.
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const ARMSubtarget *Subtarget;
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/// AFI - Keep a pointer to ARMFunctionInfo for the current
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/// MachineFunction.
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ARMFunctionInfo *AFI;
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/// MCP - Keep a pointer to constantpool entries of the current
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/// MachineFunction.
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const MachineConstantPool *MCP;
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public:
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explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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}
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virtual const char *getPassName() const {
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return "ARM Assembly Printer";
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}
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void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
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const char *Modifier = 0);
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virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant,
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const char *ExtraCode, raw_ostream &O);
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void EmitJumpTable(const MachineInstr *MI);
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void EmitJump2Table(const MachineInstr *MI);
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virtual void EmitInstruction(const MachineInstr *MI);
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bool runOnMachineFunction(MachineFunction &F);
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virtual void EmitConstantPool() {} // we emit constant pools customly!
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virtual void EmitFunctionEntryLabel();
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void EmitStartOfAsmFile(Module &M);
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void EmitEndOfAsmFile(Module &M);
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private:
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// Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
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void emitAttributes();
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// Helper for ELF .o only
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void emitARMAttributeSection();
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public:
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void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
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MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
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MachineLocation Location;
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assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
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// Frame address. Currently handles register +- offset only.
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if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
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Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
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else {
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DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
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}
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return Location;
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}
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virtual unsigned getISAEncoding() {
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// ARM/Darwin adds ISA to the DWARF info for each function.
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if (!Subtarget->isTargetDarwin())
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return 0;
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return Subtarget->isThumb() ?
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llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
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}
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MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
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const MachineBasicBlock *MBB) const;
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MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
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MCSymbol *GetARMSJLJEHLabel(void) const;
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/// EmitMachineConstantPoolValue - Print a machine constantpool value to
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/// the .s file.
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virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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EmitMachineConstantPoolValue(MCPV, OS);
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OutStreamer.EmitRawText(OS.str());
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}
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void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
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raw_ostream &O) {
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switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
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case 1: O << MAI->getData8bitsDirective(0); break;
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case 2: O << MAI->getData16bitsDirective(0); break;
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case 4: O << MAI->getData32bitsDirective(0); break;
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default: assert(0 && "Unknown CPV size");
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}
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ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
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if (ACPV->isLSDA()) {
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O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
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} else if (ACPV->isBlockAddress()) {
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O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
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} else if (ACPV->isGlobalValue()) {
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const GlobalValue *GV = ACPV->getGV();
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bool isIndirect = Subtarget->isTargetDarwin() &&
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Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
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if (!isIndirect)
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O << *Mang->getSymbol(GV);
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else {
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// FIXME: Remove this when Darwin transition to @GOT like syntax.
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MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
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O << *Sym;
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MachineModuleInfoMachO &MMIMachO =
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MMI->getObjFileInfo<MachineModuleInfoMachO>();
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MachineModuleInfoImpl::StubValueTy &StubSym =
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GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
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MMIMachO.getGVStubEntry(Sym);
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if (StubSym.getPointer() == 0)
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StubSym = MachineModuleInfoImpl::
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StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
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}
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} else {
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assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
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O << *GetExternalSymbolSymbol(ACPV->getSymbol());
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}
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if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
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if (ACPV->getPCAdjustment() != 0) {
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O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
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<< getFunctionNumber() << "_" << ACPV->getLabelId()
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<< "+" << (unsigned)ACPV->getPCAdjustment();
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if (ACPV->mustAddCurrentAddress())
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O << "-.";
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O << ')';
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}
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}
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};
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} // end of anonymous namespace
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void ARMAsmPrinter::EmitFunctionEntryLabel() {
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if (AFI->isThumbFunction()) {
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OutStreamer.EmitRawText(StringRef("\t.code\t16"));
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if (!Subtarget->isTargetDarwin())
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OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
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else {
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// This needs to emit to a temporary string to get properly quoted
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// MCSymbols when they have spaces in them.
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SmallString<128> Tmp;
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raw_svector_ostream OS(Tmp);
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OS << "\t.thumb_func\t" << *CurrentFnSym;
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OutStreamer.EmitRawText(OS.str());
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}
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}
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OutStreamer.EmitLabel(CurrentFnSym);
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}
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/// runOnMachineFunction - This uses the EmitInstruction()
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/// method to print assembly for each instruction.
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///
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bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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AFI = MF.getInfo<ARMFunctionInfo>();
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MCP = MF.getConstantPool();
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return AsmPrinter::runOnMachineFunction(MF);
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}
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void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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raw_ostream &O, const char *Modifier) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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unsigned TF = MO.getTargetFlags();
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switch (MO.getType()) {
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default:
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assert(0 && "<unknown operand type>");
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case MachineOperand::MO_Register: {
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unsigned Reg = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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assert(!MO.getSubReg() && "Subregs should be eliminated!");
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O << ARMInstPrinter::getRegisterName(Reg);
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break;
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}
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case MachineOperand::MO_Immediate: {
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int64_t Imm = MO.getImm();
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O << '#';
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if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
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(TF == ARMII::MO_LO16))
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O << ":lower16:";
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else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
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(TF == ARMII::MO_HI16))
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O << ":upper16:";
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O << Imm;
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break;
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}
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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return;
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case MachineOperand::MO_GlobalAddress: {
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const GlobalValue *GV = MO.getGlobal();
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if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
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(TF & ARMII::MO_LO16))
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O << ":lower16:";
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else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
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(TF & ARMII::MO_HI16))
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O << ":upper16:";
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O << *Mang->getSymbol(GV);
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printOffset(MO.getOffset(), O);
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if (TF == ARMII::MO_PLT)
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O << "(PLT)";
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break;
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}
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case MachineOperand::MO_ExternalSymbol: {
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O << *GetExternalSymbolSymbol(MO.getSymbolName());
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if (TF == ARMII::MO_PLT)
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O << "(PLT)";
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break;
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}
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case MachineOperand::MO_ConstantPoolIndex:
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O << *GetCPISymbol(MO.getIndex());
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break;
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case MachineOperand::MO_JumpTableIndex:
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O << *GetJTISymbol(MO.getIndex());
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break;
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}
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}
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//===--------------------------------------------------------------------===//
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MCSymbol *ARMAsmPrinter::
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GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
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const MachineBasicBlock *MBB) const {
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SmallString<60> Name;
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raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
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<< getFunctionNumber() << '_' << uid << '_' << uid2
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<< "_set_" << MBB->getNumber();
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return OutContext.GetOrCreateSymbol(Name.str());
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}
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MCSymbol *ARMAsmPrinter::
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GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
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SmallString<60> Name;
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raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
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<< getFunctionNumber() << '_' << uid << '_' << uid2;
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return OutContext.GetOrCreateSymbol(Name.str());
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}
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MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
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SmallString<60> Name;
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raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
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<< getFunctionNumber();
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return OutContext.GetOrCreateSymbol(Name.str());
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}
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bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0) return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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default: return true; // Unknown modifier.
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case 'a': // Print as a memory address.
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if (MI->getOperand(OpNum).isReg()) {
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O << "["
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<< ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
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<< "]";
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return false;
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}
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// Fallthrough
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case 'c': // Don't print "#" before an immediate operand.
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if (!MI->getOperand(OpNum).isImm())
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return true;
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O << MI->getOperand(OpNum).getImm();
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return false;
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case 'P': // Print a VFP double precision register.
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case 'q': // Print a NEON quad precision register.
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printOperand(MI, OpNum, O);
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return false;
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case 'Q':
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case 'R':
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case 'H':
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report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
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return true;
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}
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}
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printOperand(MI, OpNum, O);
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return false;
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}
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bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNum, unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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const MachineOperand &MO = MI->getOperand(OpNum);
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assert(MO.isReg() && "unexpected inline asm memory operand");
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O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
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return false;
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}
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void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
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if (Subtarget->isTargetDarwin()) {
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Reloc::Model RelocM = TM.getRelocationModel();
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if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
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// Declare all the text sections up front (before the DWARF sections
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// emitted by AsmPrinter::doInitialization) so the assembler will keep
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// them together at the beginning of the object file. This helps
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// avoid out-of-range branches that are due a fundamental limitation of
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// the way symbol offsets are encoded with the current Darwin ARM
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// relocations.
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const TargetLoweringObjectFileMachO &TLOFMacho =
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static_cast<const TargetLoweringObjectFileMachO &>(
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getObjFileLowering());
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OutStreamer.SwitchSection(TLOFMacho.getTextSection());
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OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
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OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
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if (RelocM == Reloc::DynamicNoPIC) {
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const MCSection *sect =
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OutContext.getMachOSection("__TEXT", "__symbol_stub4",
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MCSectionMachO::S_SYMBOL_STUBS,
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12, SectionKind::getText());
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OutStreamer.SwitchSection(sect);
|
|
} else {
|
|
const MCSection *sect =
|
|
OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
|
|
MCSectionMachO::S_SYMBOL_STUBS,
|
|
16, SectionKind::getText());
|
|
OutStreamer.SwitchSection(sect);
|
|
}
|
|
const MCSection *StaticInitSect =
|
|
OutContext.getMachOSection("__TEXT", "__StaticInit",
|
|
MCSectionMachO::S_REGULAR |
|
|
MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
|
|
SectionKind::getText());
|
|
OutStreamer.SwitchSection(StaticInitSect);
|
|
}
|
|
}
|
|
|
|
// Use unified assembler syntax.
|
|
OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
|
|
|
|
// Emit ARM Build Attributes
|
|
if (Subtarget->isTargetELF()) {
|
|
|
|
emitAttributes();
|
|
}
|
|
}
|
|
|
|
|
|
void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
|
|
if (Subtarget->isTargetDarwin()) {
|
|
// All darwin targets use mach-o.
|
|
const TargetLoweringObjectFileMachO &TLOFMacho =
|
|
static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
|
|
MachineModuleInfoMachO &MMIMacho =
|
|
MMI->getObjFileInfo<MachineModuleInfoMachO>();
|
|
|
|
// Output non-lazy-pointers for external and common global variables.
|
|
MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
|
|
|
|
if (!Stubs.empty()) {
|
|
// Switch with ".non_lazy_symbol_pointer" directive.
|
|
OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
|
|
EmitAlignment(2);
|
|
for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
|
|
// L_foo$stub:
|
|
OutStreamer.EmitLabel(Stubs[i].first);
|
|
// .indirect_symbol _foo
|
|
MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
|
|
OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
|
|
|
|
if (MCSym.getInt())
|
|
// External to current translation unit.
|
|
OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
|
|
else
|
|
// Internal to current translation unit.
|
|
//
|
|
// When we place the LSDA into the TEXT section, the type info
|
|
// pointers need to be indirect and pc-rel. We accomplish this by
|
|
// using NLPs; however, sometimes the types are local to the file.
|
|
// We need to fill in the value for the NLP in those cases.
|
|
OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
|
|
OutContext),
|
|
4/*size*/, 0/*addrspace*/);
|
|
}
|
|
|
|
Stubs.clear();
|
|
OutStreamer.AddBlankLine();
|
|
}
|
|
|
|
Stubs = MMIMacho.GetHiddenGVStubList();
|
|
if (!Stubs.empty()) {
|
|
OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
|
|
EmitAlignment(2);
|
|
for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
|
|
// L_foo$stub:
|
|
OutStreamer.EmitLabel(Stubs[i].first);
|
|
// .long _foo
|
|
OutStreamer.EmitValue(MCSymbolRefExpr::
|
|
Create(Stubs[i].second.getPointer(),
|
|
OutContext),
|
|
4/*size*/, 0/*addrspace*/);
|
|
}
|
|
|
|
Stubs.clear();
|
|
OutStreamer.AddBlankLine();
|
|
}
|
|
|
|
// Funny Darwin hack: This flag tells the linker that no global symbols
|
|
// contain code that falls through to other global symbols (e.g. the obvious
|
|
// implementation of multiple entry points). If this doesn't occur, the
|
|
// linker can safely perform dead code stripping. Since LLVM never
|
|
// generates code that does this, it is always safe to set.
|
|
OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
|
|
// FIXME:
|
|
// The following seem like one-off assembler flags, but they actually need
|
|
// to appear in the .ARM.attributes section in ELF.
|
|
// Instead of subclassing the MCELFStreamer, we do the work here.
|
|
|
|
void ARMAsmPrinter::emitAttributes() {
|
|
|
|
emitARMAttributeSection();
|
|
|
|
AttributeEmitter *AttrEmitter;
|
|
if (OutStreamer.hasRawTextSupport())
|
|
AttrEmitter = new AsmAttributeEmitter(OutStreamer);
|
|
else {
|
|
MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
|
|
AttrEmitter = new ObjectAttributeEmitter(O);
|
|
}
|
|
|
|
AttrEmitter->MaybeSwitchVendor("aeabi");
|
|
|
|
std::string CPUString = Subtarget->getCPUString();
|
|
if (OutStreamer.hasRawTextSupport()) {
|
|
if (CPUString != "generic")
|
|
OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
|
|
} else {
|
|
assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
|
|
// FIXME: Why these defaults?
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
|
|
}
|
|
|
|
// FIXME: Emit FPU type
|
|
if (Subtarget->hasVFP2())
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
|
|
|
|
// Signal various FP modes.
|
|
if (!UnsafeFPMath) {
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
|
|
}
|
|
|
|
if (NoInfsFPMath && NoNaNsFPMath)
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
|
|
else
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
|
|
|
|
// 8-bytes alignment stuff.
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
|
|
|
|
// Hard float. Use both S and D registers and conform to AAPCS-VFP.
|
|
if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
|
|
}
|
|
// FIXME: Should we signal R9 usage?
|
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
|
|
|
|
AttrEmitter->Finish();
|
|
delete AttrEmitter;
|
|
}
|
|
|
|
void ARMAsmPrinter::emitARMAttributeSection() {
|
|
// <format-version>
|
|
// [ <section-length> "vendor-name"
|
|
// [ <file-tag> <size> <attribute>*
|
|
// | <section-tag> <size> <section-number>* 0 <attribute>*
|
|
// | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
|
|
// ]+
|
|
// ]*
|
|
|
|
if (OutStreamer.hasRawTextSupport())
|
|
return;
|
|
|
|
const ARMElfTargetObjectFile &TLOFELF =
|
|
static_cast<const ARMElfTargetObjectFile &>
|
|
(getObjFileLowering());
|
|
|
|
OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
|
|
|
|
// Format version
|
|
OutStreamer.EmitIntValue(0x41, 1);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
|
|
unsigned LabelId, MCContext &Ctx) {
|
|
|
|
MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
|
|
+ "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
|
|
return Label;
|
|
}
|
|
|
|
void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
|
|
unsigned Opcode = MI->getOpcode();
|
|
int OpNum = 1;
|
|
if (Opcode == ARM::BR_JTadd)
|
|
OpNum = 2;
|
|
else if (Opcode == ARM::BR_JTm)
|
|
OpNum = 3;
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
|
|
unsigned JTI = MO1.getIndex();
|
|
|
|
// Emit a label for the jump table.
|
|
MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
|
|
OutStreamer.EmitLabel(JTISymbol);
|
|
|
|
// Emit each entry of the table.
|
|
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
|
|
|
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
|
|
MachineBasicBlock *MBB = JTBBs[i];
|
|
// Construct an MCExpr for the entry. We want a value of the form:
|
|
// (BasicBlockAddr - TableBeginAddr)
|
|
//
|
|
// For example, a table with entries jumping to basic blocks BB0 and BB1
|
|
// would look like:
|
|
// LJTI_0_0:
|
|
// .word (LBB0 - LJTI_0_0)
|
|
// .word (LBB1 - LJTI_0_0)
|
|
const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
|
|
|
|
if (TM.getRelocationModel() == Reloc::PIC_)
|
|
Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
|
|
OutContext),
|
|
OutContext);
|
|
OutStreamer.EmitValue(Expr, 4);
|
|
}
|
|
}
|
|
|
|
void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
|
|
unsigned Opcode = MI->getOpcode();
|
|
int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
|
|
unsigned JTI = MO1.getIndex();
|
|
|
|
// Emit a label for the jump table.
|
|
MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
|
|
OutStreamer.EmitLabel(JTISymbol);
|
|
|
|
// Emit each entry of the table.
|
|
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
|
unsigned OffsetWidth = 4;
|
|
if (MI->getOpcode() == ARM::t2TBB)
|
|
OffsetWidth = 1;
|
|
else if (MI->getOpcode() == ARM::t2TBH)
|
|
OffsetWidth = 2;
|
|
|
|
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
|
|
MachineBasicBlock *MBB = JTBBs[i];
|
|
const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
|
|
OutContext);
|
|
// If this isn't a TBB or TBH, the entries are direct branch instructions.
|
|
if (OffsetWidth == 4) {
|
|
MCInst BrInst;
|
|
BrInst.setOpcode(ARM::t2B);
|
|
BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
|
|
OutStreamer.EmitInstruction(BrInst);
|
|
continue;
|
|
}
|
|
// Otherwise it's an offset from the dispatch instruction. Construct an
|
|
// MCExpr for the entry. We want a value of the form:
|
|
// (BasicBlockAddr - TableBeginAddr) / 2
|
|
//
|
|
// For example, a TBB table with entries jumping to basic blocks BB0 and BB1
|
|
// would look like:
|
|
// LJTI_0_0:
|
|
// .byte (LBB0 - LJTI_0_0) / 2
|
|
// .byte (LBB1 - LJTI_0_0) / 2
|
|
const MCExpr *Expr =
|
|
MCBinaryExpr::CreateSub(MBBSymbolExpr,
|
|
MCSymbolRefExpr::Create(JTISymbol, OutContext),
|
|
OutContext);
|
|
Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
|
|
OutContext);
|
|
OutStreamer.EmitValue(Expr, OffsetWidth);
|
|
}
|
|
|
|
// Make sure the instruction that follows TBB is 2-byte aligned.
|
|
// FIXME: Constant island pass should insert an "ALIGN" instruction instead.
|
|
if (MI->getOpcode() == ARM::t2TBB)
|
|
EmitAlignment(1);
|
|
}
|
|
|
|
void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
|
|
raw_ostream &OS) {
|
|
unsigned NOps = MI->getNumOperands();
|
|
assert(NOps==4);
|
|
OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
|
|
// cast away const; DIetc do not take const operands for some reason.
|
|
DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
|
|
OS << V.getName();
|
|
OS << " <- ";
|
|
// Frame address. Currently handles register +- offset only.
|
|
assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
|
|
OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
|
|
OS << ']';
|
|
OS << "+";
|
|
printOperand(MI, NOps-2, OS);
|
|
}
|
|
|
|
void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
|
ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
|
|
switch (MI->getOpcode()) {
|
|
case ARM::t2MOVi32imm:
|
|
assert(0 && "Should be lowered by thumb2it pass");
|
|
default: break;
|
|
case ARM::DBG_VALUE: {
|
|
if (isVerbose() && OutStreamer.hasRawTextSupport()) {
|
|
SmallString<128> TmpStr;
|
|
raw_svector_ostream OS(TmpStr);
|
|
PrintDebugValueComment(MI, OS);
|
|
OutStreamer.EmitRawText(StringRef(OS.str()));
|
|
}
|
|
return;
|
|
}
|
|
case ARM::tPICADD: {
|
|
// This is a pseudo op for a label + instruction sequence, which looks like:
|
|
// LPC0:
|
|
// add r0, pc
|
|
// This adds the address of LPC0 to r0.
|
|
|
|
// Emit the label.
|
|
OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
|
|
getFunctionNumber(), MI->getOperand(2).getImm(),
|
|
OutContext));
|
|
|
|
// Form and emit the add.
|
|
MCInst AddInst;
|
|
AddInst.setOpcode(ARM::tADDhirr);
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
// Add predicate operands.
|
|
AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
AddInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(AddInst);
|
|
return;
|
|
}
|
|
case ARM::PICADD: {
|
|
// This is a pseudo op for a label + instruction sequence, which looks like:
|
|
// LPC0:
|
|
// add r0, pc, r0
|
|
// This adds the address of LPC0 to r0.
|
|
|
|
// Emit the label.
|
|
OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
|
|
getFunctionNumber(), MI->getOperand(2).getImm(),
|
|
OutContext));
|
|
|
|
// Form and emit the add.
|
|
MCInst AddInst;
|
|
AddInst.setOpcode(ARM::ADDrr);
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
|
|
// Add predicate operands.
|
|
AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
|
|
// Add 's' bit operand (always reg0 for this)
|
|
AddInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(AddInst);
|
|
return;
|
|
}
|
|
case ARM::PICSTR:
|
|
case ARM::PICSTRB:
|
|
case ARM::PICSTRH:
|
|
case ARM::PICLDR:
|
|
case ARM::PICLDRB:
|
|
case ARM::PICLDRH:
|
|
case ARM::PICLDRSB:
|
|
case ARM::PICLDRSH: {
|
|
// This is a pseudo op for a label + instruction sequence, which looks like:
|
|
// LPC0:
|
|
// OP r0, [pc, r0]
|
|
// The LCP0 label is referenced by a constant pool entry in order to get
|
|
// a PC-relative address at the ldr instruction.
|
|
|
|
// Emit the label.
|
|
OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
|
|
getFunctionNumber(), MI->getOperand(2).getImm(),
|
|
OutContext));
|
|
|
|
// Form and emit the load
|
|
unsigned Opcode;
|
|
switch (MI->getOpcode()) {
|
|
default:
|
|
llvm_unreachable("Unexpected opcode!");
|
|
case ARM::PICSTR: Opcode = ARM::STRrs; break;
|
|
case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
|
|
case ARM::PICSTRH: Opcode = ARM::STRH; break;
|
|
case ARM::PICLDR: Opcode = ARM::LDRrs; break;
|
|
case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
|
|
case ARM::PICLDRH: Opcode = ARM::LDRH; break;
|
|
case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
|
|
case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
|
|
}
|
|
MCInst LdStInst;
|
|
LdStInst.setOpcode(Opcode);
|
|
LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
|
|
LdStInst.addOperand(MCOperand::CreateImm(0));
|
|
// Add predicate operands.
|
|
LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
|
|
LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
|
|
OutStreamer.EmitInstruction(LdStInst);
|
|
|
|
return;
|
|
}
|
|
case ARM::CONSTPOOL_ENTRY: {
|
|
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
|
|
/// in the function. The first operand is the ID# for this instruction, the
|
|
/// second is the index into the MachineConstantPool that this is, the third
|
|
/// is the size in bytes of this constant pool entry.
|
|
unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
|
|
unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
|
|
|
|
EmitAlignment(2);
|
|
OutStreamer.EmitLabel(GetCPISymbol(LabelId));
|
|
|
|
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
|
|
if (MCPE.isMachineConstantPoolEntry())
|
|
EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
|
|
else
|
|
EmitGlobalConstant(MCPE.Val.ConstVal);
|
|
|
|
return;
|
|
}
|
|
case ARM::MOVi2pieces: {
|
|
// FIXME: We'd like to remove the asm string in the .td file, but the
|
|
// This is a hack that lowers as a two instruction sequence.
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
|
|
|
|
unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
|
|
unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
|
|
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::MOVi);
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg));
|
|
TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
|
|
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::ORRri);
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
|
|
TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
return;
|
|
}
|
|
case ARM::MOVi32imm: {
|
|
// FIXME: We'd like to remove the asm string in the .td file, but the
|
|
// This is a hack that lowers as a two instruction sequence.
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
const MachineOperand &MO = MI->getOperand(1);
|
|
MCOperand V1, V2;
|
|
if (MO.isImm()) {
|
|
unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
|
|
V1 = MCOperand::CreateImm(ImmVal & 65535);
|
|
V2 = MCOperand::CreateImm(ImmVal >> 16);
|
|
} else if (MO.isGlobal()) {
|
|
MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
|
|
const MCSymbolRefExpr *SymRef1 =
|
|
MCSymbolRefExpr::Create(Symbol,
|
|
MCSymbolRefExpr::VK_ARM_LO16, OutContext);
|
|
const MCSymbolRefExpr *SymRef2 =
|
|
MCSymbolRefExpr::Create(Symbol,
|
|
MCSymbolRefExpr::VK_ARM_HI16, OutContext);
|
|
V1 = MCOperand::CreateExpr(SymRef1);
|
|
V2 = MCOperand::CreateExpr(SymRef2);
|
|
} else {
|
|
// FIXME: External symbol?
|
|
MI->dump();
|
|
llvm_unreachable("cannot handle this operand");
|
|
}
|
|
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::MOVi16);
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
|
|
TmpInst.addOperand(V1); // lower16(imm)
|
|
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::MOVTi16);
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
|
|
TmpInst.addOperand(V2); // upper16(imm)
|
|
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
|
|
return;
|
|
}
|
|
case ARM::t2TBB:
|
|
case ARM::t2TBH:
|
|
case ARM::t2BR_JT: {
|
|
// Lower and emit the instruction itself, then the jump table following it.
|
|
MCInst TmpInst;
|
|
MCInstLowering.Lower(MI, TmpInst);
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
EmitJump2Table(MI);
|
|
return;
|
|
}
|
|
case ARM::tBR_JTr:
|
|
case ARM::BR_JTr:
|
|
case ARM::BR_JTm:
|
|
case ARM::BR_JTadd: {
|
|
// Lower and emit the instruction itself, then the jump table following it.
|
|
MCInst TmpInst;
|
|
MCInstLowering.Lower(MI, TmpInst);
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
EmitJumpTable(MI);
|
|
return;
|
|
}
|
|
case ARM::TRAP: {
|
|
// Non-Darwin binutils don't yet support the "trap" mnemonic.
|
|
// FIXME: Remove this special case when they do.
|
|
if (!Subtarget->isTargetDarwin()) {
|
|
//.long 0xe7ffdefe @ trap
|
|
uint32_t Val = 0xe7ffdefeUL;
|
|
OutStreamer.AddComment("trap");
|
|
OutStreamer.EmitIntValue(Val, 4);
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
case ARM::tTRAP: {
|
|
// Non-Darwin binutils don't yet support the "trap" mnemonic.
|
|
// FIXME: Remove this special case when they do.
|
|
if (!Subtarget->isTargetDarwin()) {
|
|
//.short 57086 @ trap
|
|
uint16_t Val = 0xdefe;
|
|
OutStreamer.AddComment("trap");
|
|
OutStreamer.EmitIntValue(Val, 2);
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
case ARM::t2Int_eh_sjlj_setjmp:
|
|
case ARM::t2Int_eh_sjlj_setjmp_nofp:
|
|
case ARM::tInt_eh_sjlj_setjmp: {
|
|
// Two incoming args: GPR:$src, GPR:$val
|
|
// mov $val, pc
|
|
// adds $val, #7
|
|
// str $val, [$src, #4]
|
|
// movs r0, #0
|
|
// b 1f
|
|
// movs r0, #1
|
|
// 1:
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
unsigned ValReg = MI->getOperand(1).getReg();
|
|
MCSymbol *Label = GetARMSJLJEHLabel();
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
// 's' bit operand
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
|
OutStreamer.AddComment("eh_setjmp begin");
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tADDi3);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
// 's' bit operand
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
TmpInst.addOperand(MCOperand::CreateImm(7));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tSTR);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
// The offset immediate is #4. The operand value is scaled by 4 for the
|
|
// tSTR instruction.
|
|
TmpInst.addOperand(MCOperand::CreateImm(1));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tMOVi8);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tB);
|
|
TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tMOVi8);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
|
TmpInst.addOperand(MCOperand::CreateImm(1));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.AddComment("eh_setjmp end");
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
OutStreamer.EmitLabel(Label);
|
|
return;
|
|
}
|
|
|
|
case ARM::Int_eh_sjlj_setjmp_nofp:
|
|
case ARM::Int_eh_sjlj_setjmp: {
|
|
// Two incoming args: GPR:$src, GPR:$val
|
|
// add $val, pc, #8
|
|
// str $val, [$src, #+4]
|
|
// mov r0, #0
|
|
// add pc, pc, #0
|
|
// mov r0, #1
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
unsigned ValReg = MI->getOperand(1).getReg();
|
|
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::ADDri);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
TmpInst.addOperand(MCOperand::CreateImm(8));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
// 's' bit operand (always reg0 for this).
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.AddComment("eh_setjmp begin");
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::STRi12);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
TmpInst.addOperand(MCOperand::CreateImm(4));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::MOVi);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
// 's' bit operand (always reg0 for this).
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::ADDri);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
// 's' bit operand (always reg0 for this).
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::MOVi);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(1));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
// 's' bit operand (always reg0 for this).
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.AddComment("eh_setjmp end");
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
return;
|
|
}
|
|
case ARM::Int_eh_sjlj_longjmp: {
|
|
// ldr sp, [$src, #8]
|
|
// ldr $scratch, [$src, #4]
|
|
// ldr r7, [$src]
|
|
// bx $scratch
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
unsigned ScratchReg = MI->getOperand(1).getReg();
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::LDRi12);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
TmpInst.addOperand(MCOperand::CreateImm(8));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::LDRi12);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
TmpInst.addOperand(MCOperand::CreateImm(4));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::LDRi12);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::BRIND);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
return;
|
|
}
|
|
case ARM::tInt_eh_sjlj_longjmp: {
|
|
// ldr $scratch, [$src, #8]
|
|
// mov sp, $scratch
|
|
// ldr $scratch, [$src, #4]
|
|
// ldr r7, [$src]
|
|
// bx $scratch
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
unsigned ScratchReg = MI->getOperand(1).getReg();
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tLDR);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
// The offset immediate is #8. The operand value is scaled by 4 for the
|
|
// tSTR instruction.
|
|
TmpInst.addOperand(MCOperand::CreateImm(2));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tLDR);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
TmpInst.addOperand(MCOperand::CreateImm(1));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tLDR);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
{
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(ARM::tBX_RET_vararg);
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
// Predicate.
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
|
|
MCInst TmpInst;
|
|
MCInstLowering.Lower(MI, TmpInst);
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target Registry Stuff
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
static MCInstPrinter *createARMMCInstPrinter(const Target &T,
|
|
unsigned SyntaxVariant,
|
|
const MCAsmInfo &MAI) {
|
|
if (SyntaxVariant == 0)
|
|
return new ARMInstPrinter(MAI);
|
|
return 0;
|
|
}
|
|
|
|
// Force static initialization.
|
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extern "C" void LLVMInitializeARMAsmPrinter() {
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RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
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RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
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TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
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}
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