Tim Northover 291cd09645 ARM64: make sure FastISel emits SSA MachineInstrs ... We need to use a temporary register for a 2-step operation like REM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208297 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-08 10:30:56 +00:00
..
Analysis	Revert "SCEV: Use I = vector<>.erase(I) to iterate and delete at the same time"	2014-05-08 07:55:34 +00:00
AsmParser	IR: Don't allow non-default visibility on local linkage	2014-05-07 22:57:20 +00:00
Bitcode	IR: Don't allow non-default visibility on local linkage	2014-05-07 22:57:20 +00:00
CodeGen	Move late partial-unrolling thresholds into the processor definitions	2014-05-08 09:14:44 +00:00
DebugInfo
ExecutionEngine	Back out r208257 while I investigate tester failures.	2014-05-07 23:35:53 +00:00
IR	llvm-cov: Explicitly namespace llvm::make_unique to keep MSVC happy	2014-05-07 16:01:27 +00:00
IRReader
LineEditor
Linker	LTO: Assert visibility of local linkage when merging symbols	2014-05-07 22:55:46 +00:00
LTO	LTO: Check local linkage first	2014-05-07 22:53:14 +00:00
MC	Remove the UseCFI option from createAsmStreamer.	2014-05-07 13:00:43 +00:00
Object	[yaml2obj] Support ELF x86 relocations.	2014-05-07 17:06:38 +00:00
Option
ProfileData
Support
TableGen	Use a vector of unique_ptrs to fix a memory leak introduced in r208179.	2014-05-08 09:29:28 +00:00
Target	ARM64: make sure FastISel emits SSA MachineInstrs	2014-05-08 10:30:56 +00:00
Transforms	Simplify and fix incorrect comment. No functionality change.	2014-05-08 01:08:43 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile