mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2926869b4a
actually *removes* one of the operands, instead of just assigning both operands the same register. This make reasoning about instructions unnecessarily complex, because you need to know if you are before or after register allocation to match up operand #'s with the target description file. Changing this also gets rid of a bunch of hacky code in various places. This patch also includes changes to fold loads into cmp/test instructions in the X86 backend, along with a significant simplification to the X86 spill folding code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30108 91177308-0d34-0410-b5e6-96231b3b80d8
267 lines
9.9 KiB
C++
267 lines
9.9 KiB
C++
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstrInfo.h"
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#include "X86.h"
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#include "X86GenInstrInfo.inc"
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#include "X86InstrBuilder.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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: TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])),
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TM(tm), RI(*this) {
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}
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bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
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oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
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oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
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oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
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oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
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oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
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oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
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oc == X86::MOVDI2PDIrr || oc == X86::MOVQI2PQIrr ||
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oc == X86::MOVPDI2DIrr) {
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid register-register move instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case X86::MOV8rm:
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case X86::MOV16rm:
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case X86::MOV16_rm:
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case X86::MOV32rm:
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case X86::MOV32_rm:
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case X86::FpLD64m:
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case X86::MOVSSrm:
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case X86::MOVSDrm:
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case X86::MOVAPSrm:
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case X86::MOVAPDrm:
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if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
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MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 1 &&
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MI->getOperand(3).getReg() == 0 &&
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MI->getOperand(4).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case X86::MOV8mr:
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case X86::MOV16mr:
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case X86::MOV16_mr:
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case X86::MOV32mr:
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case X86::MOV32_mr:
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case X86::FpSTP64m:
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case X86::MOVSSmr:
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case X86::MOVSDmr:
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case X86::MOVAPSmr:
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case X86::MOVAPDmr:
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if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
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MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
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MI->getOperand(1).getImmedValue() == 1 &&
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MI->getOperand(2).getReg() == 0 &&
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MI->getOperand(3).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(0).getFrameIndex();
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return MI->getOperand(4).getReg();
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}
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break;
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}
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return 0;
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}
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
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// All instructions input are two-addr instructions. Get the known operands.
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Src = MI->getOperand(1).getReg();
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switch (MI->getOpcode()) {
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default: break;
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case X86::SHUFPSrri: {
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assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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unsigned A = MI->getOperand(0).getReg();
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unsigned B = MI->getOperand(1).getReg();
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unsigned C = MI->getOperand(2).getReg();
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unsigned M = MI->getOperand(3).getImmedValue();
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if (!Subtarget->hasSSE2() || B != C) return 0;
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return BuildMI(X86::PSHUFDri, 2, A).addReg(B).addImm(M);
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}
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}
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// FIXME: None of these instructions are promotable to LEAs without
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// additional information. In particular, LEA doesn't set the flags that
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// add and inc do. :(
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return 0;
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// FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
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// we have subtarget support, enable the 16-bit LEA generation here.
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bool DisableLEA16 = true;
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switch (MI->getOpcode()) {
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case X86::INC32r:
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assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
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return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
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case X86::INC16r:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
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return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
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case X86::DEC32r:
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assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
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return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
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case X86::DEC16r:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
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return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
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case X86::ADD32rr:
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
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MI->getOperand(2).getReg());
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case X86::ADD16rr:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
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MI->getOperand(2).getReg());
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case X86::ADD32ri:
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case X86::ADD32ri8:
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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if (MI->getOperand(2).isImmediate())
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return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
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MI->getOperand(2).getImmedValue());
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return 0;
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case X86::ADD16ri:
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case X86::ADD16ri8:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
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if (MI->getOperand(2).isImmediate())
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return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
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MI->getOperand(2).getImmedValue());
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break;
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case X86::SHL16ri:
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if (DisableLEA16) return 0;
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case X86::SHL32ri:
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assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
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"Unknown shl instruction!");
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unsigned ShAmt = MI->getOperand(2).getImmedValue();
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if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
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X86AddressMode AM;
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AM.Scale = 1 << ShAmt;
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AM.IndexReg = Src;
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unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
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return addFullAddress(BuildMI(Opc, 5, Dest), AM);
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}
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break;
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}
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return 0;
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}
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commute them.
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///
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MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
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case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
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case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
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case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
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unsigned Opc;
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unsigned Size;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
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case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
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case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
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case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
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}
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unsigned Amt = MI->getOperand(3).getImmedValue();
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unsigned A = MI->getOperand(0).getReg();
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unsigned B = MI->getOperand(1).getReg();
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unsigned C = MI->getOperand(2).getReg();
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return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
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}
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default:
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return TargetInstrInfo::commuteInstruction(MI);
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}
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}
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void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
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MachineBasicBlock& TMBB) const {
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BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
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}
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MachineBasicBlock::iterator
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X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
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unsigned Opcode = MI->getOpcode();
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assert(isBranch(Opcode) && "MachineInstr must be a branch");
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unsigned ROpcode;
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switch (Opcode) {
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default: assert(0 && "Cannot reverse unconditional branches!");
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case X86::JB: ROpcode = X86::JAE; break;
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case X86::JAE: ROpcode = X86::JB; break;
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case X86::JE: ROpcode = X86::JNE; break;
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case X86::JNE: ROpcode = X86::JE; break;
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case X86::JBE: ROpcode = X86::JA; break;
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case X86::JA: ROpcode = X86::JBE; break;
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case X86::JS: ROpcode = X86::JNS; break;
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case X86::JNS: ROpcode = X86::JS; break;
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case X86::JP: ROpcode = X86::JNP; break;
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case X86::JNP: ROpcode = X86::JP; break;
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case X86::JL: ROpcode = X86::JGE; break;
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case X86::JGE: ROpcode = X86::JL; break;
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case X86::JLE: ROpcode = X86::JG; break;
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case X86::JG: ROpcode = X86::JLE; break;
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}
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MachineBasicBlock* MBB = MI->getParent();
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MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
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return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
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}
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