llvm-6502/lib/CodeGen
2010-02-21 20:28:15 +00:00
..
AsmPrinter move isOnlyReachableByFallthrough out of MachineBasicBlock into AsmPrinter, 2010-02-17 18:52:56 +00:00
PBQP * Updated the cost matrix normalization proceedure to better handle infinite costs. 2010-02-12 09:43:37 +00:00
SelectionDAG Revert commits 96556 and 96640, because commit 96556 breaks the 2010-02-19 11:30:41 +00:00
AggressiveAntiDepBreaker.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
AggressiveAntiDepBreaker.h 80 column and whitespace cleanup 2010-01-06 16:48:02 +00:00
AntiDepBreaker.h
BranchFolding.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
BranchFolding.h
CalcSpillWeights.cpp Always normalize spill weights, also for intervals created by spilling. 2010-02-18 21:33:05 +00:00
CMakeLists.txt Add missed entry to cmake build list file 2010-02-15 22:55:13 +00:00
CodePlacementOpt.cpp Make CodePlacementOpt detect special EH control flow by 2010-02-18 21:25:53 +00:00
CriticalAntiDepBreaker.cpp Anti-dependency breaking needs to be careful regarding instructions with 2010-01-06 22:21:25 +00:00
CriticalAntiDepBreaker.h Anti-dependency breaking needs to be careful regarding instructions with 2010-01-06 22:21:25 +00:00
DeadMachineInstructionElim.cpp Rewrite handling of DBG_VALUE; previous algorithm 2010-02-12 18:40:17 +00:00
DwarfEHPrepare.cpp SjLj EH introduces can introduce an additional edge to a landing pad and pad 2010-01-20 23:03:55 +00:00
ELF.h
ELFCodeEmitter.cpp prep work to support a future where getJumpTableInfo will return 2010-01-25 23:22:00 +00:00
ELFCodeEmitter.h
ELFWriter.cpp remove dead #include, stupid symlinks. 2010-02-02 22:37:42 +00:00
ELFWriter.h
ExactHazardRecognizer.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
ExactHazardRecognizer.h
GCMetadata.cpp Change errs() to dbgs(). 2010-01-04 21:35:15 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
IfConversion.cpp Change errs() to dbgs(). 2010-01-04 22:02:01 +00:00
IntrinsicLowering.cpp Uniformize the names of type predicates: rather than having isFloatTy and 2010-02-15 16:12:20 +00:00
LatencyPriorityQueue.cpp
LiveInterval.cpp Fix a comment typo. 2010-01-12 22:18:56 +00:00
LiveIntervalAnalysis.cpp Always normalize spill weights, also for intervals created by spilling. 2010-02-18 21:33:05 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
LLVMTargetMachine.cpp Besides removing phi cycles that reduce to a single value, also remove dead 2010-02-13 00:31:44 +00:00
LowerSubregs.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
MachineBasicBlock.cpp move isOnlyReachableByFallthrough out of MachineBasicBlock into AsmPrinter, 2010-02-17 18:52:56 +00:00
MachineDominators.cpp
MachineFunction.cpp Add support for the 'alignstack' attribute to the x86 backend. Fixes PR5254. 2010-02-19 18:17:13 +00:00
MachineFunctionAnalysis.cpp make MachineFunction keep track of its ID and make 2010-01-26 04:35:26 +00:00
MachineFunctionPass.cpp
MachineInstr.cpp Add non-temporal flags to MachineMemOperand. 2010-02-15 16:48:31 +00:00
MachineLICM.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
MachineLoopInfo.cpp Restore dump() methods to Loop and MachineLoop. 2010-01-05 21:08:02 +00:00
MachineModuleInfo.cpp Fix an uninitialized value. Radar 7609421. 2010-02-06 05:55:20 +00:00
MachineModuleInfoImpls.cpp Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there 2010-02-15 22:35:59 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
MachineSSAUpdater.cpp fix missing #includes. 2010-02-10 01:17:36 +00:00
MachineVerifier.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
Makefile make -fno-rtti the default unless a directory builds with REQUIRES_RTTI. 2010-01-24 20:43:08 +00:00
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizeExts.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
OptimizePHIs.cpp Besides removing phi cycles that reduce to a single value, also remove dead 2010-02-13 00:31:44 +00:00
Passes.cpp Uniformize the way these options are printed. Requested by 2010-02-18 14:37:52 +00:00
PHIElimination.cpp Dead code elimination. 2010-02-17 19:13:56 +00:00
PHIElimination.h Dead code elimination. 2010-02-17 19:13:56 +00:00
PostRASchedulerList.cpp Change errs() to dbgs(). 2010-01-05 01:26:01 +00:00
PreAllocSplitting.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
ProcessImplicitDefs.cpp Fix PR6300. 2010-02-15 22:03:29 +00:00
PrologEpilogInserter.cpp Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in 2010-02-19 18:59:53 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocLinearScan.cpp Change errs() to dbgs(). 2010-01-05 01:25:20 +00:00
RegAllocLocal.cpp Reapply 96294; now that I've gotten around to looking 2010-02-16 01:27:47 +00:00
RegAllocPBQP.cpp Remove terminating dot in description. Inconsistency pointed 2010-02-18 14:10:41 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp
ScheduleDAG.cpp Change errs() to dbgs(). 2010-01-05 01:25:41 +00:00
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp There are two ways of checking for a given type, for example isa<PointerType>(T) 2010-02-16 11:11:14 +00:00
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp Change errs() to dbgs(). 2010-01-05 01:25:39 +00:00
SimpleHazardRecognizer.h
SimpleRegisterCoalescing.cpp Enable assertion to detect cyclic valno references. 2010-02-21 18:51:48 +00:00
SimpleRegisterCoalescing.h
SjLjEHPrepare.cpp Update of 94055 to track the IR level call site information via an intrinsic. 2010-01-28 01:45:32 +00:00
SlotIndexes.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
Spiller.cpp Change errs() to dbgs(). 2010-01-05 01:25:55 +00:00
Spiller.h
StackProtector.cpp Uniformize the names of type predicates: rather than having isFloatTy and 2010-02-15 16:12:20 +00:00
StackSlotColoring.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
StrongPHIElimination.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
TailDuplication.cpp Reuse operand location when updating PHI instructions. 2010-02-11 00:34:33 +00:00
TargetInstrInfoImpl.cpp Add Target hook to duplicate machine instructions. 2010-01-06 23:47:07 +00:00
TargetLoweringObjectFileImpl.cpp It turned out that we failed to emit proper symbol stubs on non-x86/darwin for ages (we emitted a reference to a stub, but no stub was emitted). The code inside x86-32/macho target objfile lowering should actually be the generic one - move it there. 2010-02-21 20:28:15 +00:00
TwoAddressInstructionPass.cpp Don't allow DBG_VALUE to affect codegen. 2010-02-11 18:22:31 +00:00
UnreachableBlockElim.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
VirtRegMap.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
VirtRegMap.h
VirtRegRewriter.cpp Uniformize the way these options are printed. Requested by 2010-02-18 14:37:52 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.