Evan Cheng 298ebf2bd8 If the false case is the current basic block, then this is a self loop. ... We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra instruction in the loop. Instead, invert the condition and emit "Loop: ... br!cond Loop; br Out. Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8		2006-02-16 08:27:56 +00:00
..
DAGCombiner.cpp	Lowering of sdiv X, pow2 was broken, this fixes it. This patch is written	2006-02-16 08:02:36 +00:00
LegalizeDAG.cpp	Should not combine ISD::LOCATIONs until we have scheme to remove from	2006-02-15 19:34:44 +00:00
Makefile
ScheduleDAG.cpp	Make MachineConstantPool entries alignments explicit	2006-02-09 02:23:13 +00:00
ScheduleDAGList.cpp	make -debug output less newliney	2006-02-02 00:38:08 +00:00
ScheduleDAGSimple.cpp	Fix VC++ compilation error.	2006-01-24 04:43:17 +00:00
SelectionDAG.cpp	Added SelectionDAG::InsertISelMapEntry(). This is used to workaround the gcc	2006-02-09 22:11:03 +00:00
SelectionDAGISel.cpp	If the false case is the current basic block, then this is a self loop.	2006-02-16 08:27:56 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp	Rename maxStoresPerMemSet to maxStoresPerMemset, etc.	2006-02-14 08:38:30 +00:00