Richard Sandiford 299fdd814f [SystemZ] Add TM and TMY ... The main complication here is that TM and TMY (the memory forms) set CC differently from the register forms. When the tested bits contain some 0s and some 1s, the register forms set CC to 1 or 2 based on the value the uppermost bit. The memory forms instead set CC to 1 regardless of the uppermost bit. Until now, I've tried to make it so that a branch never tests for an impossible CC value. E.g. NR only sets CC to 0 or 1, so branches on the result will only test for 0 or 1. Originally I'd tried to do the same thing for TM and TMY by using custom matching code in ISelDAGToDAG. That ended up being very ugly though, and would have meant duplicating some of the chain checks that the common isel code does. I've therefore gone for the simpler alternative of adding an extra operand to the TM DAG opcode to say whether a memory form would be OK. This means that the inverse of a "TM;JE" is "TM;JNE" rather than the more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE". I suppose that's arguably less confusing though... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190400 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-10 10:20:32 +00:00
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AArch64	Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,	2013-09-09 02:20:27 +00:00
ARM	[ARMv8] Add some missing tests for DSB/DMB.	2013-09-05 16:05:45 +00:00
Mips	This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.	2013-09-06 13:08:00 +00:00
SystemZ	[SystemZ] Add TM and TMY	2013-09-10 10:20:32 +00:00
X86	Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode.	2013-08-30 21:19:48 +00:00
XCore	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00