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https://github.com/c64scene-ar/llvm-6502.git
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dd0fb018a7
Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182704 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.2 KiB
LLVM
37 lines
1.2 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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;
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; PR11431: handle a phi operand that is replaced by a postinc user.
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; LSR first expands %t3 to %t2 in %phi
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; LSR then expands %t2 in %phi into two decrements, one on each loop exit.
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target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64"
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target triple = "x86_64-unknown-linux-gnu"
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declare i1 @check() nounwind
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; Check that LSR did something close to the behavior at the time of the bug.
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; CHECK: @sqlite3DropTriggerPtr
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; CHECK: incq %r{{[a-d]}}x
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; CHECK: jne
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; CHECK: decq %r{{[a-d]}}x
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; CHECK: ret
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define i64 @sqlite3DropTriggerPtr() nounwind {
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bb:
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%cmp = call zeroext i1 @check()
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br label %bb1
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bb1: ; preds = %bb4, %bb
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%t0 = phi i64 [ 0, %bb ], [ %t3, %bb4 ]
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%t2 = phi i64 [ 1, %bb ], [ %t5, %bb4 ]
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%t3 = add nsw i64 %t0, 1
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br i1 %cmp, label %bb4, label %bb8
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bb4: ; preds = %bb1
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%t5 = add nsw i64 %t2, 1
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br i1 %cmp, label %bb1, label %bb8
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bb8: ; preds = %bb8, %bb4
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%phi = phi i64 [ %t3, %bb1 ], [ %t2, %bb4 ]
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ret i64 %phi
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}
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