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function. They don't appear to be used, and are inconsistent with handling of other physreg intervals (i.e. intervals that are not live-in) where ranges are not inserted for aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148986 91177308-0d34-0410-b5e6-96231b3b80d8
948 lines
34 KiB
C++
948 lines
34 KiB
C++
//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass which is used
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// by the Linear Scan Register allocator. This pass linearizes the
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// basic blocks of the function in DFS order and uses the
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// LiveVariables pass to conservatively compute live intervals for
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// each virtual and physical register.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "VirtRegMap.h"
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#include "llvm/Value.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ProcessImplicitDefs.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include <algorithm>
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#include <limits>
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#include <cmath>
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using namespace llvm;
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// Hidden options for help debugging.
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static cl::opt<bool> DisableReMat("disable-rematerialization",
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cl::init(false), cl::Hidden);
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STATISTIC(numIntervals , "Number of original intervals");
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char LiveIntervals::ID = 0;
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INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
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"Live Interval Analysis", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveVariables)
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INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
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INITIALIZE_PASS_DEPENDENCY(PHIElimination)
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INITIALIZE_PASS_DEPENDENCY(TwoAddressInstructionPass)
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INITIALIZE_PASS_DEPENDENCY(ProcessImplicitDefs)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
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"Live Interval Analysis", false, false)
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void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<AliasAnalysis>();
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AU.addRequired<LiveVariables>();
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AU.addPreserved<LiveVariables>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreservedID(MachineDominatorsID);
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if (!StrongPHIElim) {
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AU.addPreservedID(PHIEliminationID);
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AU.addRequiredID(PHIEliminationID);
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}
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AU.addRequiredID(TwoAddressInstructionPassID);
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AU.addPreserved<ProcessImplicitDefs>();
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AU.addRequired<ProcessImplicitDefs>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequiredTransitive<SlotIndexes>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void LiveIntervals::releaseMemory() {
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// Free the live intervals themselves.
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for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
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E = r2iMap_.end(); I != E; ++I)
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delete I->second;
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r2iMap_.clear();
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// Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
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VNInfoAllocator.Reset();
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while (!CloneMIs.empty()) {
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MachineInstr *MI = CloneMIs.back();
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CloneMIs.pop_back();
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mf_->DeleteMachineInstr(MI);
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}
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}
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/// runOnMachineFunction - Register allocate the whole function
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///
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bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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mri_ = &mf_->getRegInfo();
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tm_ = &fn.getTarget();
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tri_ = tm_->getRegisterInfo();
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tii_ = tm_->getInstrInfo();
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aa_ = &getAnalysis<AliasAnalysis>();
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lv_ = &getAnalysis<LiveVariables>();
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indexes_ = &getAnalysis<SlotIndexes>();
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allocatableRegs_ = tri_->getAllocatableSet(fn);
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computeIntervals();
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numIntervals += getNumIntervals();
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DEBUG(dump());
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return true;
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}
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/// print - Implement the dump method.
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void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
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OS << "********** INTERVALS **********\n";
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for (const_iterator I = begin(), E = end(); I != E; ++I) {
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I->second->print(OS, tri_);
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OS << "\n";
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}
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printInstrs(OS);
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}
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void LiveIntervals::printInstrs(raw_ostream &OS) const {
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OS << "********** MACHINEINSTRS **********\n";
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mf_->print(OS, indexes_);
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}
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void LiveIntervals::dumpInstrs() const {
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printInstrs(dbgs());
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}
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static
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bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
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unsigned Reg = MI.getOperand(MOIdx).getReg();
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for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg())
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continue;
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if (MO.getReg() == Reg && MO.isDef()) {
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assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
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MI.getOperand(MOIdx).getSubReg() &&
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(MO.getSubReg() || MO.isImplicit()));
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return true;
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}
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}
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return false;
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}
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/// isPartialRedef - Return true if the specified def at the specific index is
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/// partially re-defining the specified live interval. A common case of this is
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/// a definition of the sub-register.
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bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
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LiveInterval &interval) {
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if (!MO.getSubReg() || MO.isEarlyClobber())
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return false;
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SlotIndex RedefIndex = MIIdx.getRegSlot();
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const LiveRange *OldLR =
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interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
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MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
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if (DefMI != 0) {
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return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
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}
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return false;
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}
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void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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MachineBasicBlock::iterator mi,
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SlotIndex MIIdx,
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MachineOperand& MO,
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unsigned MOIdx,
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LiveInterval &interval) {
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DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
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// Virtual registers may be defined multiple times (due to phi
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// elimination and 2-addr elimination). Much of what we do only has to be
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// done once for the vreg. We use an empty interval to detect the first
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// time we see a vreg.
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LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
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if (interval.empty()) {
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// Get the Idx of the defining instructions.
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SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
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// Make sure the first definition is not a partial redefinition. Add an
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// <imp-def> of the full register.
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// FIXME: LiveIntervals shouldn't modify the code like this. Whoever
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// created the machine instruction should annotate it with <undef> flags
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// as needed. Then we can simply assert here. The REG_SEQUENCE lowering
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// is the main suspect.
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if (MO.getSubReg()) {
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mi->addRegisterDefined(interval.reg);
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// Mark all defs of interval.reg on this instruction as reading <undef>.
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for (unsigned i = MOIdx, e = mi->getNumOperands(); i != e; ++i) {
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MachineOperand &MO2 = mi->getOperand(i);
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if (MO2.isReg() && MO2.getReg() == interval.reg && MO2.getSubReg())
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MO2.setIsUndef();
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}
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}
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MachineInstr *CopyMI = NULL;
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if (mi->isCopyLike()) {
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CopyMI = mi;
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}
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VNInfo *ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
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assert(ValNo->id == 0 && "First value in interval is not 0?");
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// Loop over all of the blocks that the vreg is defined in. There are
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// two cases we have to handle here. The most common case is a vreg
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// whose lifetime is contained within a basic block. In this case there
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// will be a single kill, in MBB, which comes after the definition.
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if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
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// FIXME: what about dead vars?
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SlotIndex killIdx;
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if (vi.Kills[0] != mi)
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killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
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else
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killIdx = defIndex.getDeadSlot();
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// If the kill happens after the definition, we have an intra-block
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// live range.
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if (killIdx > defIndex) {
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assert(vi.AliveBlocks.empty() &&
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"Shouldn't be alive across any blocks!");
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LiveRange LR(defIndex, killIdx, ValNo);
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interval.addRange(LR);
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DEBUG(dbgs() << " +" << LR << "\n");
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return;
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}
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}
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// The other case we handle is when a virtual register lives to the end
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// of the defining block, potentially live across some blocks, then is
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// live into some number of blocks, but gets killed. Start by adding a
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// range that goes from this definition to the end of the defining block.
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LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
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DEBUG(dbgs() << " +" << NewLR);
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interval.addRange(NewLR);
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bool PHIJoin = lv_->isPHIJoin(interval.reg);
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if (PHIJoin) {
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// A phi join register is killed at the end of the MBB and revived as a new
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// valno in the killing blocks.
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assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
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DEBUG(dbgs() << " phi-join");
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ValNo->setHasPHIKill(true);
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} else {
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// Iterate over all of the blocks that the variable is completely
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// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
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// live interval.
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for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
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E = vi.AliveBlocks.end(); I != E; ++I) {
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MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
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LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
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interval.addRange(LR);
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DEBUG(dbgs() << " +" << LR);
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}
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}
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// Finally, this virtual register is live from the start of any killing
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// block to the 'use' slot of the killing instruction.
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for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
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MachineInstr *Kill = vi.Kills[i];
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SlotIndex Start = getMBBStartIdx(Kill->getParent());
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SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
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// Create interval with one of a NEW value number. Note that this value
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// number isn't actually defined by an instruction, weird huh? :)
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if (PHIJoin) {
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assert(getInstructionFromIndex(Start) == 0 &&
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"PHI def index points at actual instruction.");
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ValNo = interval.getNextValue(Start, 0, VNInfoAllocator);
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ValNo->setIsPHIDef(true);
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}
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LiveRange LR(Start, killIdx, ValNo);
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interval.addRange(LR);
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DEBUG(dbgs() << " +" << LR);
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}
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} else {
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if (MultipleDefsBySameMI(*mi, MOIdx))
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// Multiple defs of the same virtual register by the same instruction.
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// e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
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// This is likely due to elimination of REG_SEQUENCE instructions. Return
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// here since there is nothing to do.
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return;
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// If this is the second time we see a virtual register definition, it
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// must be due to phi elimination or two addr elimination. If this is
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// the result of two address elimination, then the vreg is one of the
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// def-and-use register operand.
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// It may also be partial redef like this:
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// 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
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// 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
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bool PartReDef = isPartialRedef(MIIdx, MO, interval);
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if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
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// If this is a two-address definition, then we have already processed
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// the live range. The only problem is that we didn't realize there
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// are actually two values in the live interval. Because of this we
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// need to take the LiveRegion that defines this register and split it
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// into two values.
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SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
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const LiveRange *OldLR =
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interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
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VNInfo *OldValNo = OldLR->valno;
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SlotIndex DefIndex = OldValNo->def.getRegSlot();
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// Delete the previous value, which should be short and continuous,
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// because the 2-addr copy must be in the same MBB as the redef.
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interval.removeRange(DefIndex, RedefIndex);
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// The new value number (#1) is defined by the instruction we claimed
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// defined value #0.
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VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
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// Value#0 is now defined by the 2-addr instruction.
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OldValNo->def = RedefIndex;
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OldValNo->setCopy(0);
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// A re-def may be a copy. e.g. %reg1030:6<def> = VMOVD %reg1026, ...
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if (PartReDef && mi->isCopyLike())
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OldValNo->setCopy(&*mi);
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// Add the new live interval which replaces the range for the input copy.
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LiveRange LR(DefIndex, RedefIndex, ValNo);
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DEBUG(dbgs() << " replace range with " << LR);
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interval.addRange(LR);
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// If this redefinition is dead, we need to add a dummy unit live
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// range covering the def slot.
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if (MO.isDead())
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interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
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OldValNo));
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DEBUG({
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dbgs() << " RESULT: ";
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interval.print(dbgs(), tri_);
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});
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} else if (lv_->isPHIJoin(interval.reg)) {
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// In the case of PHI elimination, each variable definition is only
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// live until the end of the block. We've already taken care of the
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// rest of the live range.
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SlotIndex defIndex = MIIdx.getRegSlot();
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if (MO.isEarlyClobber())
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defIndex = MIIdx.getRegSlot(true);
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VNInfo *ValNo;
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MachineInstr *CopyMI = NULL;
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if (mi->isCopyLike())
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CopyMI = mi;
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ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
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SlotIndex killIndex = getMBBEndIdx(mbb);
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LiveRange LR(defIndex, killIndex, ValNo);
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interval.addRange(LR);
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ValNo->setHasPHIKill(true);
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DEBUG(dbgs() << " phi-join +" << LR);
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} else {
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llvm_unreachable("Multiply defined register");
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}
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}
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DEBUG(dbgs() << '\n');
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}
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|
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void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator mi,
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SlotIndex MIIdx,
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MachineOperand& MO,
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LiveInterval &interval,
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MachineInstr *CopyMI) {
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// A physical register cannot be live across basic block, so its
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// lifetime must end somewhere in its defining basic block.
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DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
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SlotIndex baseIndex = MIIdx;
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SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
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SlotIndex end = start;
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// If it is not used after definition, it is considered dead at
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// the instruction defining it. Hence its interval is:
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// [defSlot(def), defSlot(def)+1)
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// For earlyclobbers, the defSlot was pushed back one; the extra
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// advance below compensates.
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if (MO.isDead()) {
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DEBUG(dbgs() << " dead");
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end = start.getDeadSlot();
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goto exit;
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}
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// If it is not dead on definition, it must be killed by a
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// subsequent instruction. Hence its interval is:
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// [defSlot(def), useSlot(kill)+1)
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baseIndex = baseIndex.getNextIndex();
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while (++mi != MBB->end()) {
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if (mi->isDebugValue())
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continue;
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if (getInstructionFromIndex(baseIndex) == 0)
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baseIndex = indexes_->getNextNonNullIndex(baseIndex);
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if (mi->killsRegister(interval.reg, tri_)) {
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DEBUG(dbgs() << " killed");
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end = baseIndex.getRegSlot();
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goto exit;
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} else {
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int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
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if (DefIdx != -1) {
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if (mi->isRegTiedToUseOperand(DefIdx)) {
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// Two-address instruction.
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end = baseIndex.getRegSlot();
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} else {
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// Another instruction redefines the register before it is ever read.
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// Then the register is essentially dead at the instruction that
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// defines it. Hence its interval is:
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// [defSlot(def), defSlot(def)+1)
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DEBUG(dbgs() << " dead");
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end = start.getDeadSlot();
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}
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goto exit;
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}
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}
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baseIndex = baseIndex.getNextIndex();
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}
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|
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// The only case we should have a dead physreg here without a killing or
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// instruction where we know it's dead is if it is live-in to the function
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// and never used. Another possible case is the implicit use of the
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// physical register has been deleted by two-address pass.
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end = start.getDeadSlot();
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exit:
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assert(start < end && "did not find end of interval?");
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// Already exists? Extend old live interval.
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VNInfo *ValNo = interval.getVNInfoAt(start);
|
|
bool Extend = ValNo != 0;
|
|
if (!Extend)
|
|
ValNo = interval.getNextValue(start, CopyMI, VNInfoAllocator);
|
|
if (Extend && MO.isEarlyClobber())
|
|
ValNo->setHasRedefByEC(true);
|
|
LiveRange LR(start, end, ValNo);
|
|
interval.addRange(LR);
|
|
DEBUG(dbgs() << " +" << LR << '\n');
|
|
}
|
|
|
|
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
SlotIndex MIIdx,
|
|
MachineOperand& MO,
|
|
unsigned MOIdx) {
|
|
if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
|
handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
|
|
getOrCreateInterval(MO.getReg()));
|
|
else {
|
|
MachineInstr *CopyMI = NULL;
|
|
if (MI->isCopyLike())
|
|
CopyMI = MI;
|
|
handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
|
|
getOrCreateInterval(MO.getReg()), CopyMI);
|
|
}
|
|
}
|
|
|
|
void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
|
|
SlotIndex MIIdx,
|
|
LiveInterval &interval, bool isAlias) {
|
|
DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
|
|
|
|
// Look for kills, if it reaches a def before it's killed, then it shouldn't
|
|
// be considered a livein.
|
|
MachineBasicBlock::iterator mi = MBB->begin();
|
|
MachineBasicBlock::iterator E = MBB->end();
|
|
// Skip over DBG_VALUE at the start of the MBB.
|
|
if (mi != E && mi->isDebugValue()) {
|
|
while (++mi != E && mi->isDebugValue())
|
|
;
|
|
if (mi == E)
|
|
// MBB is empty except for DBG_VALUE's.
|
|
return;
|
|
}
|
|
|
|
SlotIndex baseIndex = MIIdx;
|
|
SlotIndex start = baseIndex;
|
|
if (getInstructionFromIndex(baseIndex) == 0)
|
|
baseIndex = indexes_->getNextNonNullIndex(baseIndex);
|
|
|
|
SlotIndex end = baseIndex;
|
|
bool SeenDefUse = false;
|
|
|
|
while (mi != E) {
|
|
if (mi->killsRegister(interval.reg, tri_)) {
|
|
DEBUG(dbgs() << " killed");
|
|
end = baseIndex.getRegSlot();
|
|
SeenDefUse = true;
|
|
break;
|
|
} else if (mi->definesRegister(interval.reg, tri_)) {
|
|
// Another instruction redefines the register before it is ever read.
|
|
// Then the register is essentially dead at the instruction that defines
|
|
// it. Hence its interval is:
|
|
// [defSlot(def), defSlot(def)+1)
|
|
DEBUG(dbgs() << " dead");
|
|
end = start.getDeadSlot();
|
|
SeenDefUse = true;
|
|
break;
|
|
}
|
|
|
|
while (++mi != E && mi->isDebugValue())
|
|
// Skip over DBG_VALUE.
|
|
;
|
|
if (mi != E)
|
|
baseIndex = indexes_->getNextNonNullIndex(baseIndex);
|
|
}
|
|
|
|
// Live-in register might not be used at all.
|
|
if (!SeenDefUse) {
|
|
if (isAlias) {
|
|
DEBUG(dbgs() << " dead");
|
|
end = MIIdx.getDeadSlot();
|
|
} else {
|
|
DEBUG(dbgs() << " live through");
|
|
end = getMBBEndIdx(MBB);
|
|
}
|
|
}
|
|
|
|
SlotIndex defIdx = getMBBStartIdx(MBB);
|
|
assert(getInstructionFromIndex(defIdx) == 0 &&
|
|
"PHI def index points at actual instruction.");
|
|
VNInfo *vni =
|
|
interval.getNextValue(defIdx, 0, VNInfoAllocator);
|
|
vni->setIsPHIDef(true);
|
|
LiveRange LR(start, end, vni);
|
|
|
|
interval.addRange(LR);
|
|
DEBUG(dbgs() << " +" << LR << '\n');
|
|
}
|
|
|
|
/// computeIntervals - computes the live intervals for virtual
|
|
/// registers. for some ordering of the machine instructions [1,N] a
|
|
/// live interval is an interval [i, j) where 1 <= i <= j < N for
|
|
/// which a variable is live
|
|
void LiveIntervals::computeIntervals() {
|
|
DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
|
|
<< "********** Function: "
|
|
<< ((Value*)mf_->getFunction())->getName() << '\n');
|
|
|
|
SmallVector<unsigned, 8> UndefUses;
|
|
for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
|
|
MBBI != E; ++MBBI) {
|
|
MachineBasicBlock *MBB = MBBI;
|
|
if (MBB->empty())
|
|
continue;
|
|
|
|
// Track the index of the current machine instr.
|
|
SlotIndex MIIndex = getMBBStartIdx(MBB);
|
|
DEBUG(dbgs() << "BB#" << MBB->getNumber()
|
|
<< ":\t\t# derived from " << MBB->getName() << "\n");
|
|
|
|
// Create intervals for live-ins to this BB first.
|
|
for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
|
|
LE = MBB->livein_end(); LI != LE; ++LI) {
|
|
handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
|
|
}
|
|
|
|
// Skip over empty initial indices.
|
|
if (getInstructionFromIndex(MIIndex) == 0)
|
|
MIIndex = indexes_->getNextNonNullIndex(MIIndex);
|
|
|
|
for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
|
|
MI != miEnd; ++MI) {
|
|
DEBUG(dbgs() << MIIndex << "\t" << *MI);
|
|
if (MI->isDebugValue())
|
|
continue;
|
|
|
|
// Handle defs.
|
|
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.getReg())
|
|
continue;
|
|
|
|
// handle register defs - build intervals
|
|
if (MO.isDef())
|
|
handleRegisterDef(MBB, MI, MIIndex, MO, i);
|
|
else if (MO.isUndef())
|
|
UndefUses.push_back(MO.getReg());
|
|
}
|
|
|
|
// Move to the next instr slot.
|
|
MIIndex = indexes_->getNextNonNullIndex(MIIndex);
|
|
}
|
|
}
|
|
|
|
// Create empty intervals for registers defined by implicit_def's (except
|
|
// for those implicit_def that define values which are liveout of their
|
|
// blocks.
|
|
for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
|
|
unsigned UndefReg = UndefUses[i];
|
|
(void)getOrCreateInterval(UndefReg);
|
|
}
|
|
}
|
|
|
|
LiveInterval* LiveIntervals::createInterval(unsigned reg) {
|
|
float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
|
|
return new LiveInterval(reg, Weight);
|
|
}
|
|
|
|
/// dupInterval - Duplicate a live interval. The caller is responsible for
|
|
/// managing the allocated memory.
|
|
LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
|
|
LiveInterval *NewLI = createInterval(li->reg);
|
|
NewLI->Copy(*li, mri_, getVNInfoAllocator());
|
|
return NewLI;
|
|
}
|
|
|
|
/// shrinkToUses - After removing some uses of a register, shrink its live
|
|
/// range to just the remaining uses. This method does not compute reaching
|
|
/// defs for new uses, and it doesn't remove dead defs.
|
|
bool LiveIntervals::shrinkToUses(LiveInterval *li,
|
|
SmallVectorImpl<MachineInstr*> *dead) {
|
|
DEBUG(dbgs() << "Shrink: " << *li << '\n');
|
|
assert(TargetRegisterInfo::isVirtualRegister(li->reg)
|
|
&& "Can only shrink virtual registers");
|
|
// Find all the values used, including PHI kills.
|
|
SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
|
|
|
|
// Blocks that have already been added to WorkList as live-out.
|
|
SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
|
|
|
|
// Visit all instructions reading li->reg.
|
|
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li->reg);
|
|
MachineInstr *UseMI = I.skipInstruction();) {
|
|
if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
|
|
continue;
|
|
SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
|
|
// Note: This intentionally picks up the wrong VNI in case of an EC redef.
|
|
// See below.
|
|
VNInfo *VNI = li->getVNInfoBefore(Idx);
|
|
if (!VNI) {
|
|
// This shouldn't happen: readsVirtualRegister returns true, but there is
|
|
// no live value. It is likely caused by a target getting <undef> flags
|
|
// wrong.
|
|
DEBUG(dbgs() << Idx << '\t' << *UseMI
|
|
<< "Warning: Instr claims to read non-existent value in "
|
|
<< *li << '\n');
|
|
continue;
|
|
}
|
|
// Special case: An early-clobber tied operand reads and writes the
|
|
// register one slot early. The getVNInfoBefore call above would have
|
|
// picked up the value defined by UseMI. Adjust the kill slot and value.
|
|
if (SlotIndex::isSameInstr(VNI->def, Idx)) {
|
|
Idx = VNI->def;
|
|
VNI = li->getVNInfoBefore(Idx);
|
|
assert(VNI && "Early-clobber tied value not available");
|
|
}
|
|
WorkList.push_back(std::make_pair(Idx, VNI));
|
|
}
|
|
|
|
// Create a new live interval with only minimal live segments per def.
|
|
LiveInterval NewLI(li->reg, 0);
|
|
for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
|
|
I != E; ++I) {
|
|
VNInfo *VNI = *I;
|
|
if (VNI->isUnused())
|
|
continue;
|
|
NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
|
|
}
|
|
|
|
// Keep track of the PHIs that are in use.
|
|
SmallPtrSet<VNInfo*, 8> UsedPHIs;
|
|
|
|
// Extend intervals to reach all uses in WorkList.
|
|
while (!WorkList.empty()) {
|
|
SlotIndex Idx = WorkList.back().first;
|
|
VNInfo *VNI = WorkList.back().second;
|
|
WorkList.pop_back();
|
|
const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
|
|
SlotIndex BlockStart = getMBBStartIdx(MBB);
|
|
|
|
// Extend the live range for VNI to be live at Idx.
|
|
if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
|
|
(void)ExtVNI;
|
|
assert(ExtVNI == VNI && "Unexpected existing value number");
|
|
// Is this a PHIDef we haven't seen before?
|
|
if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
|
|
continue;
|
|
// The PHI is live, make sure the predecessors are live-out.
|
|
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
|
if (!LiveOut.insert(*PI))
|
|
continue;
|
|
SlotIndex Stop = getMBBEndIdx(*PI);
|
|
// A predecessor is not required to have a live-out value for a PHI.
|
|
if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
|
|
WorkList.push_back(std::make_pair(Stop, PVNI));
|
|
}
|
|
continue;
|
|
}
|
|
|
|
// VNI is live-in to MBB.
|
|
DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
|
|
NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
|
|
|
|
// Make sure VNI is live-out from the predecessors.
|
|
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
|
if (!LiveOut.insert(*PI))
|
|
continue;
|
|
SlotIndex Stop = getMBBEndIdx(*PI);
|
|
assert(li->getVNInfoBefore(Stop) == VNI &&
|
|
"Wrong value out of predecessor");
|
|
WorkList.push_back(std::make_pair(Stop, VNI));
|
|
}
|
|
}
|
|
|
|
// Handle dead values.
|
|
bool CanSeparate = false;
|
|
for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
|
|
I != E; ++I) {
|
|
VNInfo *VNI = *I;
|
|
if (VNI->isUnused())
|
|
continue;
|
|
LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
|
|
assert(LII != NewLI.end() && "Missing live range for PHI");
|
|
if (LII->end != VNI->def.getDeadSlot())
|
|
continue;
|
|
if (VNI->isPHIDef()) {
|
|
// This is a dead PHI. Remove it.
|
|
VNI->setIsUnused(true);
|
|
NewLI.removeRange(*LII);
|
|
DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
|
|
CanSeparate = true;
|
|
} else {
|
|
// This is a dead def. Make sure the instruction knows.
|
|
MachineInstr *MI = getInstructionFromIndex(VNI->def);
|
|
assert(MI && "No instruction defining live value");
|
|
MI->addRegisterDead(li->reg, tri_);
|
|
if (dead && MI->allDefsAreDead()) {
|
|
DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
|
|
dead->push_back(MI);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Move the trimmed ranges back.
|
|
li->ranges.swap(NewLI.ranges);
|
|
DEBUG(dbgs() << "Shrunk: " << *li << '\n');
|
|
return CanSeparate;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register allocator hooks.
|
|
//
|
|
|
|
void LiveIntervals::addKillFlags() {
|
|
for (iterator I = begin(), E = end(); I != E; ++I) {
|
|
unsigned Reg = I->first;
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
continue;
|
|
if (mri_->reg_nodbg_empty(Reg))
|
|
continue;
|
|
LiveInterval *LI = I->second;
|
|
|
|
// Every instruction that kills Reg corresponds to a live range end point.
|
|
for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
|
|
++RI) {
|
|
// A block index indicates an MBB edge.
|
|
if (RI->end.isBlock())
|
|
continue;
|
|
MachineInstr *MI = getInstructionFromIndex(RI->end);
|
|
if (!MI)
|
|
continue;
|
|
MI->addRegisterKilled(Reg, NULL);
|
|
}
|
|
}
|
|
}
|
|
|
|
/// getReMatImplicitUse - If the remat definition MI has one (for now, we only
|
|
/// allow one) virtual register operand, then its uses are implicitly using
|
|
/// the register. Returns the virtual register.
|
|
unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
|
|
MachineInstr *MI) const {
|
|
unsigned RegOp = 0;
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isUse())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0 || Reg == li.reg)
|
|
continue;
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
|
|
!allocatableRegs_[Reg])
|
|
continue;
|
|
RegOp = MO.getReg();
|
|
break; // Found vreg operand - leave the loop.
|
|
}
|
|
return RegOp;
|
|
}
|
|
|
|
/// isValNoAvailableAt - Return true if the val# of the specified interval
|
|
/// which reaches the given instruction also reaches the specified use index.
|
|
bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
|
|
SlotIndex UseIdx) const {
|
|
VNInfo *UValNo = li.getVNInfoAt(UseIdx);
|
|
return UValNo && UValNo == li.getVNInfoAt(getInstructionIndex(MI));
|
|
}
|
|
|
|
/// isReMaterializable - Returns true if the definition MI of the specified
|
|
/// val# of the specified interval is re-materializable.
|
|
bool
|
|
LiveIntervals::isReMaterializable(const LiveInterval &li,
|
|
const VNInfo *ValNo, MachineInstr *MI,
|
|
const SmallVectorImpl<LiveInterval*> *SpillIs,
|
|
bool &isLoad) {
|
|
if (DisableReMat)
|
|
return false;
|
|
|
|
if (!tii_->isTriviallyReMaterializable(MI, aa_))
|
|
return false;
|
|
|
|
// Target-specific code can mark an instruction as being rematerializable
|
|
// if it has one virtual reg use, though it had better be something like
|
|
// a PIC base register which is likely to be live everywhere.
|
|
unsigned ImpUse = getReMatImplicitUse(li, MI);
|
|
if (ImpUse) {
|
|
const LiveInterval &ImpLi = getInterval(ImpUse);
|
|
for (MachineRegisterInfo::use_nodbg_iterator
|
|
ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end();
|
|
ri != re; ++ri) {
|
|
MachineInstr *UseMI = &*ri;
|
|
SlotIndex UseIdx = getInstructionIndex(UseMI);
|
|
if (li.getVNInfoAt(UseIdx) != ValNo)
|
|
continue;
|
|
if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
|
|
return false;
|
|
}
|
|
|
|
// If a register operand of the re-materialized instruction is going to
|
|
// be spilled next, then it's not legal to re-materialize this instruction.
|
|
if (SpillIs)
|
|
for (unsigned i = 0, e = SpillIs->size(); i != e; ++i)
|
|
if (ImpUse == (*SpillIs)[i]->reg)
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
/// isReMaterializable - Returns true if every definition of MI of every
|
|
/// val# of the specified interval is re-materializable.
|
|
bool
|
|
LiveIntervals::isReMaterializable(const LiveInterval &li,
|
|
const SmallVectorImpl<LiveInterval*> *SpillIs,
|
|
bool &isLoad) {
|
|
isLoad = false;
|
|
for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
|
|
i != e; ++i) {
|
|
const VNInfo *VNI = *i;
|
|
if (VNI->isUnused())
|
|
continue; // Dead val#.
|
|
// Is the def for the val# rematerializable?
|
|
MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
|
|
if (!ReMatDefMI)
|
|
return false;
|
|
bool DefIsLoad = false;
|
|
if (!ReMatDefMI ||
|
|
!isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
|
|
return false;
|
|
isLoad |= DefIsLoad;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool LiveIntervals::intervalIsInOneMBB(const LiveInterval &li) const {
|
|
LiveInterval::Ranges::const_iterator itr = li.ranges.begin();
|
|
|
|
MachineBasicBlock *mbb = indexes_->getMBBCoveringRange(itr->start, itr->end);
|
|
|
|
if (mbb == 0)
|
|
return false;
|
|
|
|
for (++itr; itr != li.ranges.end(); ++itr) {
|
|
MachineBasicBlock *mbb2 =
|
|
indexes_->getMBBCoveringRange(itr->start, itr->end);
|
|
|
|
if (mbb2 != mbb)
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
float
|
|
LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
|
|
// Limit the loop depth ridiculousness.
|
|
if (loopDepth > 200)
|
|
loopDepth = 200;
|
|
|
|
// The loop depth is used to roughly estimate the number of times the
|
|
// instruction is executed. Something like 10^d is simple, but will quickly
|
|
// overflow a float. This expression behaves like 10^d for small d, but is
|
|
// more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
|
|
// headroom before overflow.
|
|
// By the way, powf() might be unavailable here. For consistency,
|
|
// We may take pow(double,double).
|
|
float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
|
|
|
|
return (isDef + isUse) * lc;
|
|
}
|
|
|
|
LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
|
|
MachineInstr* startInst) {
|
|
LiveInterval& Interval = getOrCreateInterval(reg);
|
|
VNInfo* VN = Interval.getNextValue(
|
|
SlotIndex(getInstructionIndex(startInst).getRegSlot()),
|
|
startInst, getVNInfoAllocator());
|
|
VN->setHasPHIKill(true);
|
|
LiveRange LR(
|
|
SlotIndex(getInstructionIndex(startInst).getRegSlot()),
|
|
getMBBEndIdx(startInst->getParent()), VN);
|
|
Interval.addRange(LR);
|
|
|
|
return LR;
|
|
}
|
|
|