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mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-30 02:32:08 +00:00
llvm-6502/lib/CodeGen
Dan Gohman 29e4bdbf27 Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49666 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-14 17:55:48 +00:00
..
SelectionDAG Fix const-correctness issues with the SrcValue handling in the 2008-04-14 17:55:48 +00:00
AsmPrinter.cpp Make EH work with unnamed functions. Reenable running 2008-04-02 20:10:52 +00:00
BranchFolding.cpp Teach branch folding pass about implicit_def instructions. Unfortunately we can't just eliminate them since register scavenger expects every register use to be defined. However, we can delete them when there are no intra-block uses. Carefully removing some implicit def's which enable more blocks to be optimized away. 2008-04-10 02:32:10 +00:00
Collector.cpp
CollectorMetadata.cpp
Collectors.cpp
DwarfWriter.cpp Reverse sense of unwind-tables option. This means 2008-04-14 17:54:17 +00:00
ELFWriter.cpp
ELFWriter.h
IfConversion.cpp
IntrinsicLowering.cpp API changes for class Use size reduction, wave 1. 2008-04-06 20:25:17 +00:00
LiveInterval.cpp
LiveIntervalAnalysis.cpp Use of implicit_def is not part of live interval. Create empty intervals for the uses when the live interval is being spilled. 2008-04-11 17:53:36 +00:00
LiveVariables.cpp Now that I am told MachineRegisterInfo also tracks physical register uses / defs, I can do away with the horribleness I introduced a while back. It's impossible to detect if there is any use of a physical register below an instruction (and before any def of the register) with some cheap book keeping. 2008-04-02 18:04:08 +00:00
LLVMTargetMachine.cpp Recommitting EH patch; this should answer most of the 2008-04-02 00:25:04 +00:00
LoopAligner.cpp
LowerSubregs.cpp
MachineBasicBlock.cpp
MachineDominators.cpp
MachineFunction.cpp Silence warning when no assertions. 2008-04-06 21:46:45 +00:00
MachineInstr.cpp Rename MemOperand to MachineMemOperand. This was suggested by 2008-04-07 19:35:22 +00:00
MachineLICM.cpp
MachineLoopInfo.cpp
MachineModuleInfo.cpp Recommitting EH patch; this should answer most of the 2008-04-02 00:25:04 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp
MachOWriter.cpp
MachOWriter.h
Makefile
OcamlCollector.cpp
Passes.cpp
PHIElimination.cpp If a PHI node has a single implicit_def source, replace it with an implicit_def instead of a copy. 2008-04-11 17:54:45 +00:00
PhysRegTracker.h
PostRASchedulerList.cpp
PrologEpilogInserter.cpp
PseudoSourceValue.cpp
README.txt This is done. 2008-04-04 01:19:03 +00:00
RegAllocBigBlock.cpp
RegAllocLinearScan.cpp Do not add empty live intervals to handled_. They should never be undone for backtracking. 2008-04-11 17:55:47 +00:00
RegAllocLocal.cpp Remove #include<map> from LiveVariables.h. Not referenced. 2008-04-02 17:23:50 +00:00
RegAllocSimple.cpp Don't include <map> in Pass.h, which doesn't need it. This requires 2008-03-21 23:51:57 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp Allow registers defined by implicit_def to be clobbered. 2008-04-10 23:47:53 +00:00
ShadowStackCollector.cpp Merge LLVMBuilder and FoldingBuilder, calling 2008-04-13 06:22:09 +00:00
SimpleRegisterCoalescing.cpp Remove implicit_def instructions that become dead as result of coalescing. 2008-04-10 23:48:35 +00:00
SimpleRegisterCoalescing.h Add comment. 2008-04-10 08:03:14 +00:00
StrongPHIElimination.cpp In some situations, we need to check for local interferences between the PHI 2008-04-02 03:00:13 +00:00
TargetInstrInfoImpl.cpp Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. 2008-03-31 20:40:39 +00:00
TwoAddressInstructionPass.cpp
UnreachableBlockElim.cpp
VirtRegMap.cpp Use of implicit_def is not part of live interval. Create empty intervals for the uses when the live interval is being spilled. 2008-04-11 17:53:36 +00:00
VirtRegMap.h Use of implicit_def is not part of live interval. Create empty intervals for the uses when the live interval is being spilled. 2008-04-11 17:53:36 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
	ldr r3, [sp, #+4]
	add r3, r3, #3
	ldr r2, [sp, #+8]
	add r2, r2, #2
	ldr r1, [sp, #+4]  <==
	add r1, r1, #1
	ldr r0, [sp, #+4]
	add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.