llvm-6502/lib/Target/ARM/ARMSelectionDAGInfo.h
Andrew Trick ac6d9bec67 Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-25 02:42:55 +00:00

69 lines
2.4 KiB
C++

//===-- ARMSelectionDAGInfo.h - ARM SelectionDAG Info -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the ARM subclass for TargetSelectionDAGInfo.
//
//===----------------------------------------------------------------------===//
#ifndef ARMSELECTIONDAGINFO_H
#define ARMSELECTIONDAGINFO_H
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/Target/TargetSelectionDAGInfo.h"
namespace llvm {
namespace ARM_AM {
static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
switch (Opcode) {
default: return ARM_AM::no_shift;
case ISD::SHL: return ARM_AM::lsl;
case ISD::SRL: return ARM_AM::lsr;
case ISD::SRA: return ARM_AM::asr;
case ISD::ROTR: return ARM_AM::ror;
//case ISD::ROTL: // Only if imm -> turn into ROTR.
// Can't handle RRX here, because it would require folding a flag into
// the addressing mode. :( This causes us to miss certain things.
//case ARMISD::RRX: return ARM_AM::rrx;
}
}
} // end namespace ARM_AM
class ARMSelectionDAGInfo : public TargetSelectionDAGInfo {
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
/// make the right decision when generating code for different targets.
const ARMSubtarget *Subtarget;
public:
explicit ARMSelectionDAGInfo(const TargetMachine &TM);
~ARMSelectionDAGInfo();
virtual
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const;
// Adjust parameters for memset, see RTABI section 4.3.4
virtual
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
SDValue Chain,
SDValue Op1, SDValue Op2,
SDValue Op3, unsigned Align,
bool isVolatile,
MachinePointerInfo DstPtrInfo) const;
};
}
#endif