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Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. Patch by: Vadim Girlin Vincent Lejeune: - Use pointers for constants - Fold CONST_ADDRESS when possible Tom Stellard: - Give CONSTANT_BUFFER_0 its own address space - Use integer types for constant loads Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173222 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.5 KiB
C++
86 lines
2.5 KiB
C++
//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief R600 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "R600RegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "R600Defines.h"
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#include "R600MachineFunctionInfo.h"
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using namespace llvm;
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R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
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const TargetInstrInfo &tii)
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: AMDGPURegisterInfo(tm, tii),
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TM(tm),
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TII(tii)
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{ }
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BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const R600MachineFunctionInfo * MFI = MF.getInfo<R600MachineFunctionInfo>();
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Reserved.set(AMDGPU::ZERO);
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Reserved.set(AMDGPU::HALF);
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Reserved.set(AMDGPU::ONE);
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Reserved.set(AMDGPU::ONE_INT);
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Reserved.set(AMDGPU::NEG_HALF);
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Reserved.set(AMDGPU::NEG_ONE);
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Reserved.set(AMDGPU::PV_X);
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Reserved.set(AMDGPU::ALU_LITERAL_X);
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Reserved.set(AMDGPU::ALU_CONST);
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Reserved.set(AMDGPU::PREDICATE_BIT);
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Reserved.set(AMDGPU::PRED_SEL_OFF);
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Reserved.set(AMDGPU::PRED_SEL_ZERO);
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Reserved.set(AMDGPU::PRED_SEL_ONE);
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for (std::vector<unsigned>::const_iterator I = MFI->ReservedRegs.begin(),
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E = MFI->ReservedRegs.end(); I != E; ++I) {
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Reserved.set(*I);
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}
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return Reserved;
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}
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const TargetRegisterClass *
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R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
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switch (rc->getID()) {
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case AMDGPU::GPRF32RegClassID:
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case AMDGPU::GPRI32RegClassID:
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return &AMDGPU::R600_Reg32RegClass;
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default: return rc;
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}
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}
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unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
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return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
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}
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const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
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}
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}
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unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const {
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switch (Channel) {
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default: assert(!"Invalid channel index"); return 0;
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case 0: return AMDGPU::sel_x;
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case 1: return AMDGPU::sel_y;
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case 2: return AMDGPU::sel_z;
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case 3: return AMDGPU::sel_w;
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}
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}
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