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af4c7300b9
- 'prefetch' intrinsics are only lowered when SSE is available. On non-X86 builds, 'generic' CPU is used and stops lowering any prefetch intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178046 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
754 B
LLVM
23 lines
754 B
LLVM
; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s
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; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
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; RUN: llc < %s -march=x86 -mattr=+sse -mattr=+prfchw | FileCheck %s -check-prefix=PRFCHW
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; rdar://10538297
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define void @t(i8* %ptr) nounwind {
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entry:
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; CHECK: prefetcht2
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; CHECK: prefetcht1
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; CHECK: prefetcht0
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; CHECK: prefetchnta
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; PRFCHW: prefetchw
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
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ret void
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}
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declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
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