llvm-6502/test/CodeGen
Bill Schmidt 11729224bf [PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.
This is a preliminary patch for fast instruction selection on
PowerPC.  Code generation can differ between DAG isel and fast isel.
Existing tests that specify -O0 were written to expect DAG isel.  Make
this explicit by adding -fast-isel=false to the tests.

In some cases specifying -fast-isel=false produces different code even
when there isn't a fast instruction selector specified.  This is
because TM.Options.EnableFastISel = 1 at -O0 whether or not a FastISel
object exists.  Thus disabling fast isel can actually produce less
conservative code.  Because of this, some of the expected code
generation in the -O0 tests needs to be adjusted.

In particular, handling of function arguments is less conservative
with -fast-isel=false (see isOnlyUsedInEntryBlock() in
SelectionDAGBuilder.cpp).  This results in fewer stack accesses and,
in some cases, reduced stack size as uselessly loaded values are no
longer stored back to spill locations in the stack.

No functional change with this patch; test case adjustments only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-13 20:23:34 +00:00
..
AArch64 Change how we iterate over relocations on ELF. 2013-05-30 03:05:14 +00:00
ARM Add test for ARM FastISel load/store register classes 2013-06-10 00:35:57 +00:00
CPP
Generic Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen. 2013-05-21 14:37:16 +00:00
Hexagon
Inputs
MBlaze
Mips [mips] Add an IR transformation pass that optimizes calls to sqrt. 2013-06-11 22:21:44 +00:00
MSP430
NVPTX [NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space 2013-06-10 13:29:47 +00:00
PowerPC [PowerPC] Disable fast-isel for existing -O0 tests for PowerPC. 2013-06-13 20:23:34 +00:00
R600 R600: Anti dep better handled in tex clause 2013-06-07 23:30:26 +00:00
SI
SPARC [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 2013-06-08 15:32:59 +00:00
SystemZ [SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses 2013-05-31 13:25:22 +00:00
Thumb
Thumb2 Cortex-R5 can issue Thumb2 integer division instructions. 2013-06-04 22:52:09 +00:00
X86 X86: Stop LEA64_32r doing unspeakable things to its arguments. 2013-06-10 20:43:49 +00:00
XCore