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Someone couldn't bear to have a completely orthogonal set of floating-point registers, so we've got some instructions that only accept v0-v15 (coming in ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...). Anyway, we were permitting even the out of range registers during assembly (CodeGen handled it correctly). This adds a diagnostic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207412 91177308-0d34-0410-b5e6-96231b3b80d8