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https://github.com/c64scene-ar/llvm-6502.git
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1d09d56fe1
This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
3.3 KiB
TableGen
72 lines
3.3 KiB
TableGen
//===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Record that INSN performs a 64-bit version of unary operator OPERATOR
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// in which the operand is sign-extended from 32 to 64 bits.
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multiclass SXU<SDPatternOperator operator, Instruction insn> {
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def : Pat<(operator (sext (i32 GR32:$src))),
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(insn GR32:$src)>;
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def : Pat<(operator (sext_inreg GR64:$src, i32)),
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(insn (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
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}
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// Record that INSN performs a 64-bit version of binary operator OPERATOR
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// in which the first operand has class CLS and which the second operand
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// is sign-extended from a 32-bit register.
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multiclass SXB<SDPatternOperator operator, RegisterOperand cls,
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Instruction insn> {
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def : Pat<(operator cls:$src1, (sext GR32:$src2)),
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(insn cls:$src1, GR32:$src2)>;
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def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)),
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(insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_32bit))>;
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}
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// Like SXB, but for zero extension.
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multiclass ZXB<SDPatternOperator operator, RegisterOperand cls,
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Instruction insn> {
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def : Pat<(operator cls:$src1, (zext GR32:$src2)),
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(insn cls:$src1, GR32:$src2)>;
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def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)),
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(insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_32bit))>;
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}
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// Record that INSN performs a binary read-modify-write operation,
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// with LOAD, OPERATOR and STORE being the read, modify and write
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// respectively. MODE is the addressing mode and IMM is the type
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// of the second operand.
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class RMWI<SDPatternOperator load, SDPatternOperator operator,
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SDPatternOperator store, AddressingMode mode,
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PatFrag imm, Instruction insn>
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: Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr),
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(insn mode:$addr, (UIMM8 imm:$src))>;
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// Record that INSN performs binary operation OPERATION on a byte
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// memory location. IMM is the type of the second operand.
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multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
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Instruction insn> {
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def : RMWI<zextloadi8, operator, truncstorei8, mode, imm32, insn>;
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def : RMWI<zextloadi8, operator, truncstorei8, mode, imm64, insn>;
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def : RMWI<sextloadi8, operator, truncstorei8, mode, imm32, insn>;
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def : RMWI<sextloadi8, operator, truncstorei8, mode, imm64, insn>;
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def : RMWI<extloadi8, operator, truncstorei8, mode, imm32, insn>;
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def : RMWI<extloadi8, operator, truncstorei8, mode, imm64, insn>;
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}
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// Record that INSN performs insertion TYPE into a register of class CLS.
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// The inserted operand is loaded using LOAD from an address of mode MODE.
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multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
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SDPatternOperator load, AddressingMode mode> {
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def : Pat<(!cast<SDPatternOperator>("or_as_"##type)
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cls:$src1, (load mode:$src2)),
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(insn cls:$src1, mode:$src2)>;
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def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type)
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(load mode:$src2), cls:$src1),
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(insn cls:$src1, mode:$src2)>;
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}
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