mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
2.7 KiB
LLVM
93 lines
2.7 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define i32 @vmin_u8x8(<8 x i8> %a) nounwind ssp {
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; CHECK-LABEL: vmin_u8x8:
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; CHECK: uminv.8b b[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v8i8(<8 x i8> %a) nounwind
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%tmp = trunc i32 %vminv.i to i8
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%tobool = icmp eq i8 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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declare i32 @bar(...)
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define i32 @vmin_u4x16(<4 x i16> %a) nounwind ssp {
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; CHECK-LABEL: vmin_u4x16:
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; CHECK: uminv.4h h[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v4i16(<4 x i16> %a) nounwind
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%tmp = trunc i32 %vminv.i to i16
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%tobool = icmp eq i16 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @vmin_u8x16(<8 x i16> %a) nounwind ssp {
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; CHECK-LABEL: vmin_u8x16:
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; CHECK: uminv.8h h[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v8i16(<8 x i16> %a) nounwind
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%tmp = trunc i32 %vminv.i to i16
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%tobool = icmp eq i16 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @vmin_u16x8(<16 x i8> %a) nounwind ssp {
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; CHECK-LABEL: vmin_u16x8:
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; CHECK: uminv.16b b[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v16i8(<16 x i8> %a) nounwind
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%tmp = trunc i32 %vminv.i to i8
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%tobool = icmp eq i8 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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declare i32 @llvm.arm64.neon.uminv.i32.v16i8(<16 x i8>) nounwind readnone
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declare i32 @llvm.arm64.neon.uminv.i32.v8i16(<8 x i16>) nounwind readnone
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declare i32 @llvm.arm64.neon.uminv.i32.v4i16(<4 x i16>) nounwind readnone
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declare i32 @llvm.arm64.neon.uminv.i32.v8i8(<8 x i8>) nounwind readnone
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