mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
116 lines
5.1 KiB
LLVM
116 lines
5.1 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
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; The mask:
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; CHECK: lCPI0_0:
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; CHECK: .byte 2 ; 0x2
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; CHECK: .byte 255 ; 0xff
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; CHECK: .byte 6 ; 0x6
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; CHECK: .byte 255 ; 0xff
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; The second vector is legalized to undef and the elements of the first vector
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; are used instead.
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; CHECK: .byte 2 ; 0x2
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; CHECK: .byte 4 ; 0x4
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; CHECK: .byte 6 ; 0x6
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; CHECK: .byte 0 ; 0x0
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; CHECK: test1
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; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI0_0
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; CHECK: movi.8h v[[REG1:[0-9]+]], #1, lsl #8
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; CHECK: tbl.8b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
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define <8 x i1> @test1() {
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entry:
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%Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
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i1 7>,
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<8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
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i1 7>,
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<8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10,
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i32 12, i32 14, i32 0>
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ret <8 x i1> %Shuff
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}
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; CHECK: lCPI1_0:
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; CHECK: .byte 2 ; 0x2
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; CHECK: .byte 255 ; 0xff
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; CHECK: .byte 6 ; 0x6
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; CHECK: .byte 255 ; 0xff
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; CHECK: .byte 10 ; 0xa
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; CHECK: .byte 12 ; 0xc
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; CHECK: .byte 14 ; 0xe
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; CHECK: .byte 0 ; 0x0
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; CHECK: test2
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; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI1_0@PAGEOFF]
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; CHECK: adrp x[[REG2:[0-9]+]], lCPI1_1@PAGE
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; CHECK: ldr q[[REG1:[0-9]+]], [x[[REG2]], lCPI1_1@PAGEOFF]
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; CHECK: tbl.8b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
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define <8 x i1>@test2() {
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bb:
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%Shuff = shufflevector <8 x i1> zeroinitializer,
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<8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
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<8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
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i32 0>
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ret <8 x i1> %Shuff
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}
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; CHECK: lCPI2_0:
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; CHECK: .byte 2 ; 0x2
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; CHECK: .byte 255 ; 0xff
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; CHECK: .byte 6 ; 0x6
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; CHECK: .byte 255 ; 0xff
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; CHECK: .byte 10 ; 0xa
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; CHECK: .byte 12 ; 0xc
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; CHECK: .byte 14 ; 0xe
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 2 ; 0x2
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; CHECK: .byte 255 ; 0xff
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; CHECK: .byte 6 ; 0x6
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; CHECK: .byte 255 ; 0xff
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; CHECK: .byte 10 ; 0xa
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; CHECK: .byte 12 ; 0xc
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; CHECK: .byte 14 ; 0xe
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; CHECK: .byte 0 ; 0x0
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; CHECK: test3
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; CHECK: adrp x[[REG3:[0-9]+]], lCPI2_0@PAGE
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; CHECK: ldr q[[REG0:[0-9]+]], [x[[REG3]], lCPI2_0@PAGEOFF]
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; CHECK: movi.2d v[[REG1:[0-9]+]], #0000000000000000
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; CHECK: tbl.16b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
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define <16 x i1> @test3(i1* %ptr, i32 %v) {
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bb:
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%Shuff = shufflevector <16 x i1> zeroinitializer, <16 x i1> undef,
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<16 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
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i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12,
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i32 14, i32 0>
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ret <16 x i1> %Shuff
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}
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; CHECK: lCPI3_1:
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; CHECK: .byte 2 ; 0x2
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; CHECK: .byte 1 ; 0x1
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; CHECK: .byte 6 ; 0x6
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; CHECK: .byte 18 ; 0x12
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; CHECK: .byte 10 ; 0xa
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; CHECK: .byte 12 ; 0xc
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; CHECK: .byte 14 ; 0xe
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 2 ; 0x2
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; CHECK: .byte 31 ; 0x1f
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; CHECK: .byte 6 ; 0x6
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; CHECK: .byte 30 ; 0x1e
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; CHECK: .byte 10 ; 0xa
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; CHECK: .byte 12 ; 0xc
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; CHECK: .byte 14 ; 0xe
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; CHECK: .byte 0 ; 0x0
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; CHECK: _test4:
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; CHECK: ldr q[[REG1:[0-9]+]]
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; CHECK: movi.2d v[[REG0:[0-9]+]], #0000000000000000
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; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_1@PAGE
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; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_1@PAGEOFF]
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; CHECK: tbl.16b v{{[0-9]+}}, { v[[REG0]], v[[REG1]] }, v[[REG2]]
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define <16 x i1> @test4(i1* %ptr, i32 %v) {
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bb:
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%Shuff = shufflevector <16 x i1> zeroinitializer,
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<16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1,
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i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
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<16 x i32> <i32 2, i32 1, i32 6, i32 18, i32 10, i32 12, i32 14, i32 0,
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i32 2, i32 31, i32 6, i32 30, i32 10, i32 12, i32 14, i32 0>
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ret <16 x i1> %Shuff
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}
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