llvm-6502/test/CodeGen/ARM64/zero-cycle-zeroing.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

50 lines
1.2 KiB
LLVM

; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
; rdar://11481771
; rdar://13713797
define void @t1() nounwind ssp {
entry:
; CHECK-LABEL: t1:
; CHECK-NOT: fmov
; CHECK: movi.2d v0, #0000000000000000
; CHECK: movi.2d v1, #0000000000000000
; CHECK: movi.2d v2, #0000000000000000
; CHECK: movi.2d v3, #0000000000000000
tail call void @bar(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00) nounwind
ret void
}
define void @t2() nounwind ssp {
entry:
; CHECK-LABEL: t2:
; CHECK-NOT: mov w0, wzr
; CHECK: movz w0, #0
; CHECK: movz w1, #0
tail call void @bari(i32 0, i32 0) nounwind
ret void
}
define void @t3() nounwind ssp {
entry:
; CHECK-LABEL: t3:
; CHECK-NOT: mov x0, xzr
; CHECK: movz x0, #0
; CHECK: movz x1, #0
tail call void @barl(i64 0, i64 0) nounwind
ret void
}
define void @t4() nounwind ssp {
; CHECK-LABEL: t4:
; CHECK-NOT: fmov
; CHECK: movi.2d v0, #0000000000000000
; CHECK: movi.2d v1, #0000000000000000
tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind
ret void
}
declare void @bar(double, double, double, double)
declare void @bari(i32, i32)
declare void @barl(i64, i64)
declare void @barf(float, float)