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46f7257ed1
AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size. It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195383 91177308-0d34-0410-b5e6-96231b3b80d8
68 lines
2.4 KiB
LLVM
68 lines
2.4 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
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; clang -Oz -c test1.cpp -emit-llvm -S -o
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; Verify that we generate shld insruction when we are optimizing for size,
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; even for X86_64 processors that are known to have poor latency double
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; precision shift instuctions.
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; uint64_t lshift10(uint64_t a, uint64_t b)
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; {
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; return (a << 10) | (b >> 54);
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; }
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; Function Attrs: minsize nounwind optsize readnone uwtable
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define i64 @_Z8lshift10mm(i64 %a, i64 %b) #0 {
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entry:
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; CHECK: shldq $10
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%shl = shl i64 %a, 10
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%shr = lshr i64 %b, 54
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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attributes #0 = { minsize nounwind optsize readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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; clang -Os -c test2.cpp -emit-llvm -S
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; Verify that we generate shld insruction when we are optimizing for size,
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; even for X86_64 processors that are known to have poor latency double
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; precision shift instuctions.
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; uint64_t lshift11(uint64_t a, uint64_t b)
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; {
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; return (a << 11) | (b >> 53);
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; }
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; Function Attrs: nounwind optsize readnone uwtable
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define i64 @_Z8lshift11mm(i64 %a, i64 %b) #1 {
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entry:
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; CHECK: shldq $11
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%shl = shl i64 %a, 11
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%shr = lshr i64 %b, 53
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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attributes #1 = { nounwind optsize readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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; clang -O2 -c test2.cpp -emit-llvm -S
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; Verify that we do not generate shld insruction when we are not optimizing
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; for size for X86_64 processors that are known to have poor latency double
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; precision shift instuctions.
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; uint64_t lshift12(uint64_t a, uint64_t b)
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; {
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; return (a << 12) | (b >> 52);
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; }
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; Function Attrs: nounwind optsize readnone uwtable
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define i64 @_Z8lshift12mm(i64 %a, i64 %b) #2 {
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entry:
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; CHECK: shlq $12
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; CHECK-NEXT: shrq $52
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%shl = shl i64 %a, 12
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%shr = lshr i64 %b, 52
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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attributes #2= { nounwind readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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