llvm-6502/test/CodeGen/PowerPC/constants-i64.ll
Hal Finkel 2ac0826af3 [PowerPC] Materialize i64 constants using rotation
Materializing full 64-bit constants on PPC64 can be expensive, requiring up to
5 instructions depending on the locations of the non-zero bits. Sometimes
materializing a rotated constant, and then applying the inverse rotation, requires
fewer instructions than the direct method. If so, do that instead.

In r225132, I added support for forming constants using bit inversion. In
effect, this reverts that commit and replaces it with rotation support. The bit
inversion is useful for turning constants that are mostly ones into ones that
are mostly zeros (thus enabling a more-efficient shift-based materialization),
but the same effect can be obtained by using negative constants and a rotate,
and that is at least as efficient, if not more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225135 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-04 15:43:55 +00:00

65 lines
1.2 KiB
LLVM

; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone
define i64 @cn1() #0 {
entry:
ret i64 281474976710655
; CHECK-LABEL: @cn1
; CHECK: lis [[REG1:[0-9]+]], -1
; CHECK: rldicl 3, [[REG1]], 48, 0
; CHECK: blr
}
; Function Attrs: nounwind readnone
define i64 @cnb() #0 {
entry:
ret i64 281474976710575
; CHECK-LABEL: @cnb
; CHECK: lis [[REG1:[0-9]+]], -81
; CHECK: rldicl 3, [[REG1]], 48, 0
; CHECK: blr
}
; Function Attrs: nounwind readnone
define i64 @f2n(i64 %x) #0 {
entry:
ret i64 68719476735
; CHECK-LABEL: @f2n
; CHECK: lis [[REG1:[0-9]+]], -4096
; CHECK: rldicl 3, [[REG1]], 36, 0
; CHECK: blr
}
; Function Attrs: nounwind readnone
define i64 @f3(i64 %x) #0 {
entry:
ret i64 8589934591
; CHECK-LABEL: @f3
; CHECK: lis [[REG1:[0-9]+]], -32768
; CHECK: rldicl 3, [[REG1]], 33, 0
; CHECK: blr
}
; Function Attrs: nounwind readnone
define i64 @cn2n() #0 {
entry:
ret i64 -1407374887747585
; CHECK-LABEL: @cn2n
; CHECK: lis [[REG1:[0-9]+]], -5121
; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 65534
; CHECK: rldicl 3, [[REG2]], 22, 0
; CHECK: blr
}
attributes #0 = { nounwind readnone }