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https://github.com/c64scene-ar/llvm-6502.git
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3f409f7fef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119485 91177308-0d34-0410-b5e6-96231b3b80d8
78 lines
2.9 KiB
TableGen
78 lines
2.9 KiB
TableGen
//===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the PTX instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "PTXInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// PTX Specific Node Definitions
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//===----------------------------------------------------------------------===//
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def PTXexit
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: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
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def PTXret
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: SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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multiclass INT3<string opcstr, SDNode opnode> {
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def rr : InstPTX<(outs RRegs32:$d),
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(ins RRegs32:$a, RRegs32:$b),
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!strconcat(opcstr, ".%type\t$d, $a, $b"),
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[(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
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def ri : InstPTX<(outs RRegs32:$d),
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(ins RRegs32:$a, i32imm:$b),
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!strconcat(opcstr, ".%type\t$d, $a, $b"),
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[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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///===- Integer Arithmetic Instructions -----------------------------------===//
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defm ADD : INT3<"add", add>;
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defm SUB : INT3<"sub", sub>;
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///===- Data Movement and Conversion Instructions -------------------------===//
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let neverHasSideEffects = 1 in {
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// rely on isMoveInstr to separate MOVpp, MOVrr, etc.
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def MOVpp
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: InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
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def MOVrr
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: InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.%type\t$d, $a", []>;
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOVpi
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: InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
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[(set Preds:$d, imm:$a)]>;
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def MOVri
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: InstPTX<(outs RRegs32:$d), (ins i32imm:$a), "mov.s32\t$d, $a",
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[(set RRegs32:$d, imm:$a)]>;
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}
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///===- Control Flow Instructions -----------------------------------------===//
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
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def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
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}
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