mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2026-04-25 05:22:04 +00:00
JF Bastien
7bfd515593
Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241923 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
1.6 KiB
TableGen
44 lines
1.6 KiB
TableGen
// WebAssemblyInstrInteger.td-WebAssembly Integer codegen -------*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief WebAssembly Integer operand code-gen constructs.
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///
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//===----------------------------------------------------------------------===//
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/*
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* TODO(jfb): Add the following for 32-bit and 64-bit.
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*
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* int32.add: signed-less addition
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* int32.sub: signed-less subtraction
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* int32.mul: signed-less multiplication (lower 32-bits)
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* int32.sdiv: signed division
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* int32.udiv: unsigned division
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* int32.srem: signed remainder
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* int32.urem: unsigned remainder
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* int32.and: signed-less logical and
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* int32.ior: signed-less inclusive or
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* int32.xor: signed-less exclusive or
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* int32.shl: signed-less shift left
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* int32.shr: signed-less logical shift right
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* int32.sar: signed-less arithmetic shift right
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* int32.eq: signed-less compare equal
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* int32.slt: signed less than
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* int32.sle: signed less than or equal
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* int32.ult: unsigned less than
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* int32.ule: unsigned less than or equal
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* int32.sgt: signed greater than
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* int32.sge: signed greater than or equal
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* int32.ugt: unsigned greater than
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* int32.uge: unsigned greater than or equal
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* int32.clz: count leading zeroes (defined for all values, including zero)
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* int32.ctz: count trailing zeroes (defined for all values, including zero)
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* int32.popcnt: count number of ones
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*/
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