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https://github.com/c64scene-ar/llvm-6502.git
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8a8d479214
change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
87 lines
2.9 KiB
C++
87 lines
2.9 KiB
C++
//===-- SparcTargetMachine.h - Define TargetMachine for Sparc ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Sparc specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARCTARGETMACHINE_H
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#define SPARCTARGETMACHINE_H
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#include "SparcInstrInfo.h"
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#include "SparcISelLowering.h"
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#include "SparcFrameLowering.h"
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#include "SparcSelectionDAGInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameLowering.h"
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namespace llvm {
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class SparcTargetMachine : public LLVMTargetMachine {
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SparcSubtarget Subtarget;
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const TargetData DataLayout; // Calculates type size & alignment
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SparcTargetLowering TLInfo;
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SparcSelectionDAGInfo TSInfo;
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SparcInstrInfo InstrInfo;
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SparcFrameLowering FrameLowering;
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public:
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SparcTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool is64bit);
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virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
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virtual const TargetFrameLowering *getFrameLowering() const {
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return &FrameLowering;
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}
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virtual const SparcSubtarget *getSubtargetImpl() const{ return &Subtarget; }
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virtual const SparcRegisterInfo *getRegisterInfo() const {
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return &InstrInfo.getRegisterInfo();
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}
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virtual const SparcTargetLowering* getTargetLowering() const {
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return &TLInfo;
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}
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virtual const SparcSelectionDAGInfo* getSelectionDAGInfo() const {
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return &TSInfo;
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}
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virtual const TargetData *getTargetData() const { return &DataLayout; }
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// Pass Pipeline Configuration
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virtual bool addInstSelector(PassManagerBase &PM);
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virtual bool addPreEmitPass(PassManagerBase &PM);
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};
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/// SparcV8TargetMachine - Sparc 32-bit target machine
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///
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class SparcV8TargetMachine : public SparcTargetMachine {
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public:
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SparcV8TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// SparcV9TargetMachine - Sparc 64-bit target machine
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///
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class SparcV9TargetMachine : public SparcTargetMachine {
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public:
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SparcV9TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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