Jakob Stoklund Olesen 2afb7505c5 Teach VirtRegRewriter to handle spilling in instructions that have multiple
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:36:13 +00:00
2010-02-23 15:11:17 +00:00
2010-04-16 13:32:55 +00:00
2010-02-23 19:15:24 +00:00
2010-01-09 18:40:31 +00:00
2010-04-30 23:36:47 +00:00

Low Level Virtual Machine (LLVM)
================================

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LLVM backend for 6502
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