mirror of
https://github.com/c64scene-ar/llvm-6502.git
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33d75a269c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238858 91177308-0d34-0410-b5e6-96231b3b80d8
185 lines
6.9 KiB
ArmAsm
185 lines
6.9 KiB
ArmAsm
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s
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// RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s
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.text
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//8 bits
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casb w0, w1, [x2]
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casab w0, w1, [x2]
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caslb w0, w1, [x2]
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casalb w0, w1, [x2]
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//CHECK: casb w0, w1, [x2] // encoding: [0x41,0x7c,0xa0,0x08]
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//CHECK: casab w0, w1, [x2] // encoding: [0x41,0x7c,0xe0,0x08]
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//CHECK: caslb w0, w1, [x2] // encoding: [0x41,0xfc,0xa0,0x08]
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//CHECK: casalb w0, w1, [x2] // encoding: [0x41,0xfc,0xe0,0x08]
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casb w0, w1, [w2]
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casalb x0, x1, [x2]
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: casb w0, w1, [w2]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: casalb x0, x1, [x2]
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//CHECK-ERROR: ^
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//16 bits
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cash w0, w1, [x2]
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casah w0, w1, [x2]
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caslh w0, w1, [x2]
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casalh w0, w1, [x2]
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//CHECK: cash w0, w1, [x2] // encoding: [0x41,0x7c,0xa0,0x48]
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//CHECK: casah w0, w1, [x2] // encoding: [0x41,0x7c,0xe0,0x48]
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//CHECK: caslh w0, w1, [x2] // encoding: [0x41,0xfc,0xa0,0x48]
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//CHECK: casalh w0, w1, [x2] // encoding: [0x41,0xfc,0xe0,0x48]
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//32 bits
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cas w0, w1, [x2]
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casa w0, w1, [x2]
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casl w0, w1, [x2]
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casal w0, w1, [x2]
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//CHECK: cas w0, w1, [x2] // encoding: [0x41,0x7c,0xa0,0x88]
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//CHECK: casa w0, w1, [x2] // encoding: [0x41,0x7c,0xe0,0x88]
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//CHECK: casl w0, w1, [x2] // encoding: [0x41,0xfc,0xa0,0x88]
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//CHECK: casal w0, w1, [x2] // encoding: [0x41,0xfc,0xe0,0x88]
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cas w0, w1, [w2]
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casl w0, x1, [x2]
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: cas w0, w1, [w2]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: casl w0, x1, [x2]
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//CHECK-ERROR: ^
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//64 bits
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cas x0, x1, [x2]
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casa x0, x1, [x2]
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casl x0, x1, [x2]
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casal x0, x1, [x2]
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//CHECK: cas x0, x1, [x2] // encoding: [0x41,0x7c,0xa0,0xc8]
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//CHECK: casa x0, x1, [x2] // encoding: [0x41,0x7c,0xe0,0xc8]
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//CHECK: casl x0, x1, [x2] // encoding: [0x41,0xfc,0xa0,0xc8]
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//CHECK: casal x0, x1, [x2] // encoding: [0x41,0xfc,0xe0,0xc8]
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casa x0, x1, [w2]
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casal x0, w1, [x2]
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: casa x0, x1, [w2]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: casal x0, w1, [x2]
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//CHECK-ERROR: ^
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// LD<OP> intructions
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ldadda x0, x1, [x2]
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ldclrl x0, x1, [x2]
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ldeoral x0, x1, [x2]
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ldset x0, x1, [x2]
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ldsmaxa w0, w1, [x2]
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ldsminlb w0, w1, [x2]
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ldumaxalh w0, w1, [x2]
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ldumin w0, w1, [x2]
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ldsminb w2, w3, [x5]
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//CHECK: ldadda x0, x1, [x2] // encoding: [0x41,0x00,0xa0,0xf8]
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//CHECK: ldclrl x0, x1, [x2] // encoding: [0x41,0x10,0x60,0xf8]
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//CHECK: ldeoral x0, x1, [x2] // encoding: [0x41,0x20,0xe0,0xf8]
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//CHECK: ldset x0, x1, [x2] // encoding: [0x41,0x30,0x20,0xf8]
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//CHECK: ldsmaxa w0, w1, [x2] // encoding: [0x41,0x40,0xa0,0xb8]
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//CHECK: ldsminlb w0, w1, [x2] // encoding: [0x41,0x50,0x60,0x38]
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//CHECK: ldumaxalh w0, w1, [x2] // encoding: [0x41,0x60,0xe0,0x78]
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//CHECK: ldumin w0, w1, [x2] // encoding: [0x41,0x70,0x20,0xb8]
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//CHECK: ldsminb w2, w3, [x5] // encoding: [0xa3,0x50,0x22,0x38]
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// ST<OP> intructions: aliases to LD<OP>
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stADDlb w0, [x2]
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stclrlh w0, [x2]
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steorl w0, [x2]
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stsetl x0, [x2]
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stsmaxb w0, [x2]
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stsminh w0, [x2]
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stumax w0, [x2]
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stumin x0, [x2]
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stsminl x29, [sp]
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//CHECK: staddlb w0, [x2] // encoding: [0x5f,0x00,0x60,0x38]
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//CHECK: stclrlh w0, [x2] // encoding: [0x5f,0x10,0x60,0x78]
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//CHECK: steorl w0, [x2] // encoding: [0x5f,0x20,0x60,0xb8]
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//CHECK: stsetl x0, [x2] // encoding: [0x5f,0x30,0x60,0xf8]
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//CHECK: stsmaxb w0, [x2] // encoding: [0x5f,0x40,0x20,0x38]
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//CHECK: stsminh w0, [x2] // encoding: [0x5f,0x50,0x20,0x78]
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//CHECK: stumax w0, [x2] // encoding: [0x5f,0x60,0x20,0xb8]
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//CHECK: stumin x0, [x2] // encoding: [0x5f,0x70,0x20,0xf8]
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//CHECK: stsminl x29, [sp] // encoding: [0xff,0x53,0x7d,0xf8]
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ldsmax x0, x1, [w2]
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ldeorl w0, w1, [w2]
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: ldsmax x0, x1, [w2]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: ldeorl w0, w1, [w2]
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//CHECK-ERROR: ^
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//SWP instruction
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swp x0, x1, [x2]
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swpb w0, w1, [x2]
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swplh w0, w1, [x2]
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swpal x0, x1, [sp]
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//CHECK: swp x0, x1, [x2] // encoding: [0x41,0x80,0x20,0xf8]
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//CHECK: swpb w0, w1, [x2] // encoding: [0x41,0x80,0x20,0x38]
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//CHECK: swplh w0, w1, [x2] // encoding: [0x41,0x80,0x60,0x78]
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//CHECK: swpal x0, x1, [sp] // encoding: [0xe1,0x83,0xe0,0xf8]
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swp x0, x1, [w2]
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swp x0, x1, [xzr]
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: swp x0, x1, [w2]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: swp x0, x1, [xzr]
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//CHECK-ERROR: ^
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//CASP instruction
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casp x0, x1, x2, x3, [x4]
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casp w0, w1, w2, w3, [x4]
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//CHECK: casp x0, x1, x2, x3, [x4] // encoding: [0x82,0x7c,0x20,0x48]
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//CHECK: casp w0, w1, w2, w3, [x4] // encoding: [0x82,0x7c,0x20,0x08]
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casp x1, x2, x4, x5, [x6]
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casp x0, x1, x3, x4, [x5]
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casp x0, x2, x4, x5, [x6]
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casp x0, x1, x2, x4, [x5]
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casp x0, w1, x2, x3, [x5]
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casp w0, x1, x2, x3, [x5]
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casp w0, x1, w2, w3, [x5]
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casp x0, x1, w2, w3, [x5]
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//CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair
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//CHECK-ERROR: casp x1, x2, x4, x5, [x6]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair
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//CHECK-ERROR: casp x0, x1, x3, x4, [x5]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected second odd register of a consecutive same-size even/odd register pair
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//CHECK-ERROR: casp x0, x2, x4, x5, [x6]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected second odd register of a consecutive same-size even/odd register pair
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//CHECK-ERROR: casp x0, x1, x2, x4, [x5]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected second odd register of a consecutive same-size even/odd register pair
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//CHECK-ERROR: casp x0, w1, x2, x3, [x5]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected second odd register of a consecutive same-size even/odd register pair
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//CHECK-ERROR: casp w0, x1, x2, x3, [x5]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected second odd register of a consecutive same-size even/odd register pair
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//CHECK-ERROR: casp w0, x1, w2, w3, [x5]
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: invalid operand for instruction
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//CHECK-ERROR: casp x0, x1, w2, w3, [x5]
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//CHECK-ERROR: ^
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