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23ed37a6b7
This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
792 B
TableGen
27 lines
792 B
TableGen
//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Tablegen register definitions common to all hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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let Namespace = "AMDGPU" in {
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foreach Index = 0-15 in {
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// Indices are used in a variety of ways here, so don't set a size/offset.
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def sub#Index : SubRegIndex<-1, -1>;
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}
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def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;
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}
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include "R600RegisterInfo.td"
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include "SIRegisterInfo.td"
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