mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a23cc6a1ea
The fixes are to note that AArch64 has additional restrictions on when local relocations can be used. In particular, ld64 requires that relocations to cstring/cfstrings use linker visible symbols. Original message: In an assembly expression like bar: .long L0 + 1 the intended semantics is that bar will contain a pointer one byte past L0. In sections that are merged by content (strings, 4 byte constants, etc), a single position in the section doesn't give the linker enough information. For example, it would not be able to tell a relocation must point to the end of a string, since that would look just like the start of the next. The solution used in ELF to use relocation with symbols if there is a non-zero addend. In MachO before this patch we would just keep all symbols in some sections. This would miss some cases (only cstrings on x86_64 were implemented) and was inefficient since most relocations have an addend of 0 and can be represented without the symbol. This patch implements the non-zero addend logic for MachO too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226503 91177308-0d34-0410-b5e6-96231b3b80d8
147 lines
4.8 KiB
C++
147 lines
4.8 KiB
C++
//===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "MCTargetDesc/AMDGPUFixupKinds.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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namespace {
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class AMDGPUMCObjectWriter : public MCObjectWriter {
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public:
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AMDGPUMCObjectWriter(raw_ostream &OS) : MCObjectWriter(OS, true) { }
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void ExecutePostLayoutBinding(MCAssembler &Asm,
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const MCAsmLayout &Layout) override {
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//XXX: Implement if necessary.
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}
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void RecordRelocation(MCAssembler &Asm, const MCAsmLayout &Layout,
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const MCFragment *Fragment, const MCFixup &Fixup,
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MCValue Target, bool &IsPCRel,
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uint64_t &FixedValue) override {
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assert(!"Not implemented");
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}
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void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout) override;
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};
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class AMDGPUAsmBackend : public MCAsmBackend {
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public:
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AMDGPUAsmBackend(const Target &T)
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: MCAsmBackend() {}
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unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value, bool IsPCRel) const override;
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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return false;
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}
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
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assert(!"Not implemented");
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}
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bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
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};
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} //End anonymous namespace
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void AMDGPUMCObjectWriter::WriteObject(MCAssembler &Asm,
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const MCAsmLayout &Layout) {
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for (MCAssembler::iterator I = Asm.begin(), E = Asm.end(); I != E; ++I) {
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Asm.writeSectionData(I, Layout);
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}
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}
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void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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unsigned DataSize, uint64_t Value,
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bool IsPCRel) const {
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switch ((unsigned)Fixup.getKind()) {
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default: llvm_unreachable("Unknown fixup kind");
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case AMDGPU::fixup_si_sopp_br: {
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uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
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*Dst = (Value - 4) / 4;
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break;
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}
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case AMDGPU::fixup_si_rodata: {
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uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset());
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*Dst = Value;
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break;
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}
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case AMDGPU::fixup_si_end_of_text: {
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uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset());
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// The value points to the last instruction in the text section, so we
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// need to add 4 bytes to get to the start of the constants.
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*Dst = Value + 4;
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break;
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}
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}
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}
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const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
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MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_si_rodata", 0, 32, 0 },
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{ "fixup_si_end_of_text", 0, 32, MCFixupKindInfo::FKF_IsPCRel }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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return Infos[Kind - FirstTargetFixupKind];
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}
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bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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for (unsigned i = 0; i < Count; ++i)
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OW->Write8(0);
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return true;
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}
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//===----------------------------------------------------------------------===//
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// ELFAMDGPUAsmBackend class
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//===----------------------------------------------------------------------===//
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namespace {
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class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
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public:
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ELFAMDGPUAsmBackend(const Target &T) : AMDGPUAsmBackend(T) { }
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
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return createAMDGPUELFObjectWriter(OS);
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}
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};
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} // end anonymous namespace
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MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
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StringRef TT,
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StringRef CPU) {
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return new ELFAMDGPUAsmBackend(T);
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}
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