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https://github.com/c64scene-ar/llvm-6502.git
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ce98f09f53
These tests in particular try to use escaped square brackets as an argument to grep, which is failing for me with native win32 python. It appears the backslash is being lost near the CreateProcess*() call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173506 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
2.8 KiB
TableGen
92 lines
2.8 KiB
TableGen
// RUN: llvm-tblgen %s | FileCheck %s
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class ValueType<int size, int value> {
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int Size = size;
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int Value = value;
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}
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def f32 : ValueType<32, 1>; // 2 x i64 vector value
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class Intrinsic<string name> {
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string Name = name;
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}
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class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
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list<dag> pattern> {
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bits<8> Opcode = opcode;
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dag OutOperands = oopnds;
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dag InOperands = iopnds;
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string AssemblyString = asmstr;
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list<dag> Pattern = pattern;
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}
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def ops;
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def outs;
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def ins;
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def set;
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// Define registers
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class Register<string n> {
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string Name = n;
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}
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class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
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list<ValueType> RegTypes = regTypes;
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list<Register> MemberList = regList;
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}
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def XMM0: Register<"xmm0">;
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def XMM1: Register<"xmm1">;
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def XMM2: Register<"xmm2">;
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def XMM3: Register<"xmm3">;
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def XMM4: Register<"xmm4">;
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def XMM5: Register<"xmm5">;
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def XMM6: Register<"xmm6">;
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def XMM7: Register<"xmm7">;
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def XMM8: Register<"xmm8">;
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def XMM9: Register<"xmm9">;
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def XMM10: Register<"xmm10">;
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def XMM11: Register<"xmm11">;
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def XMM12: Register<"xmm12">;
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def XMM13: Register<"xmm13">;
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def XMM14: Register<"xmm14">;
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def XMM15: Register<"xmm15">;
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def FR32 : RegisterClass<[f32],
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11,
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XMM12, XMM13, XMM14, XMM15]>;
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class SDNode {}
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def not : SDNode;
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multiclass scalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
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def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(asmstr, "\t$dst, $src"),
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!if(!empty(patterns),[]<dag>,patterns[0])>;
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def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(asmstr, "\t$dst, $src"),
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!if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>;
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}
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multiclass vscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
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def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(asmstr, "\t$dst, $src"),
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!if(!empty(patterns),[]<dag>,patterns[0])>;
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def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(asmstr, "\t$dst, $src"),
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!if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>;
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}
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multiclass myscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> :
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scalar<opcode, asmstr, patterns>,
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vscalar<opcode, asmstr, patterns>;
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defm NOT : myscalar<0x10, "not", [[], [(set FR32:$dst, (f32 (not FR32:$src)))]]>;
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// CHECK: Pattern = [(set FR32:$dst, (f32 (not FR32:$src)))];
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// CHECK: Pattern = [];
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// CHECK: Pattern = [(set FR32:$dst, (f32 (not FR32:$src)))];
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// CHECK: Pattern = [];
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