mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-04 06:09:05 +00:00
77f268945e
This commit adds intrinsics and codegen support for the surface read/write and texture read instructions that take an explicit sampler parameter. Codegen operates on image handles at the PTX level, but falls back to direct replacement of handles with kernel arguments if image handles are not enabled. Note that image handles are explicitly disabled for all target architectures in this change (to be enabled later). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205907 91177308-0d34-0410-b5e6-96231b3b80d8
195 lines
3.6 KiB
C++
195 lines
3.6 KiB
C++
//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the entry points for global functions defined in
|
|
// the LLVM NVPTX back-end.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_TARGET_NVPTX_H
|
|
#define LLVM_TARGET_NVPTX_H
|
|
|
|
#include "MCTargetDesc/NVPTXBaseInfo.h"
|
|
#include "llvm/ADT/StringMap.h"
|
|
#include "llvm/IR/Module.h"
|
|
#include "llvm/IR/Value.h"
|
|
#include "llvm/Support/ErrorHandling.h"
|
|
#include "llvm/Target/TargetMachine.h"
|
|
#include <cassert>
|
|
#include <iosfwd>
|
|
|
|
namespace llvm {
|
|
class NVPTXTargetMachine;
|
|
class FunctionPass;
|
|
class MachineFunctionPass;
|
|
class formatted_raw_ostream;
|
|
|
|
namespace NVPTXCC {
|
|
enum CondCodes {
|
|
EQ,
|
|
NE,
|
|
LT,
|
|
LE,
|
|
GT,
|
|
GE
|
|
};
|
|
}
|
|
|
|
inline static const char *NVPTXCondCodeToString(NVPTXCC::CondCodes CC) {
|
|
switch (CC) {
|
|
case NVPTXCC::NE:
|
|
return "ne";
|
|
case NVPTXCC::EQ:
|
|
return "eq";
|
|
case NVPTXCC::LT:
|
|
return "lt";
|
|
case NVPTXCC::LE:
|
|
return "le";
|
|
case NVPTXCC::GT:
|
|
return "gt";
|
|
case NVPTXCC::GE:
|
|
return "ge";
|
|
}
|
|
llvm_unreachable("Unknown condition code");
|
|
}
|
|
|
|
FunctionPass *
|
|
createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOpt::Level OptLevel);
|
|
ModulePass *createNVPTXAssignValidGlobalNamesPass();
|
|
ModulePass *createGenericToNVVMPass();
|
|
FunctionPass *createNVPTXFavorNonGenericAddrSpacesPass();
|
|
ModulePass *createNVVMReflectPass();
|
|
ModulePass *createNVVMReflectPass(const StringMap<int>& Mapping);
|
|
MachineFunctionPass *createNVPTXPrologEpilogPass();
|
|
MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
|
|
FunctionPass *createNVPTXImageOptimizerPass();
|
|
|
|
bool isImageOrSamplerVal(const Value *, const Module *);
|
|
|
|
extern Target TheNVPTXTarget32;
|
|
extern Target TheNVPTXTarget64;
|
|
|
|
namespace NVPTX {
|
|
enum DrvInterface {
|
|
NVCL,
|
|
CUDA
|
|
};
|
|
|
|
// A field inside TSFlags needs a shift and a mask. The usage is
|
|
// always as follows :
|
|
// ((TSFlags & fieldMask) >> fieldShift)
|
|
// The enum keeps the mask, the shift, and all valid values of the
|
|
// field in one place.
|
|
enum VecInstType {
|
|
VecInstTypeShift = 0,
|
|
VecInstTypeMask = 0xF,
|
|
|
|
VecNOP = 0,
|
|
VecLoad = 1,
|
|
VecStore = 2,
|
|
VecBuild = 3,
|
|
VecShuffle = 4,
|
|
VecExtract = 5,
|
|
VecInsert = 6,
|
|
VecDest = 7,
|
|
VecOther = 15
|
|
};
|
|
|
|
enum SimpleMove {
|
|
SimpleMoveMask = 0x10,
|
|
SimpleMoveShift = 4
|
|
};
|
|
enum LoadStore {
|
|
isLoadMask = 0x20,
|
|
isLoadShift = 5,
|
|
isStoreMask = 0x40,
|
|
isStoreShift = 6
|
|
};
|
|
|
|
namespace PTXLdStInstCode {
|
|
enum AddressSpace {
|
|
GENERIC = 0,
|
|
GLOBAL = 1,
|
|
CONSTANT = 2,
|
|
SHARED = 3,
|
|
PARAM = 4,
|
|
LOCAL = 5
|
|
};
|
|
enum FromType {
|
|
Unsigned = 0,
|
|
Signed,
|
|
Float
|
|
};
|
|
enum VecType {
|
|
Scalar = 1,
|
|
V2 = 2,
|
|
V4 = 4
|
|
};
|
|
}
|
|
|
|
/// PTXCvtMode - Conversion code enumeration
|
|
namespace PTXCvtMode {
|
|
enum CvtMode {
|
|
NONE = 0,
|
|
RNI,
|
|
RZI,
|
|
RMI,
|
|
RPI,
|
|
RN,
|
|
RZ,
|
|
RM,
|
|
RP,
|
|
|
|
BASE_MASK = 0x0F,
|
|
FTZ_FLAG = 0x10,
|
|
SAT_FLAG = 0x20
|
|
};
|
|
}
|
|
|
|
/// PTXCmpMode - Comparison mode enumeration
|
|
namespace PTXCmpMode {
|
|
enum CmpMode {
|
|
EQ = 0,
|
|
NE,
|
|
LT,
|
|
LE,
|
|
GT,
|
|
GE,
|
|
LO,
|
|
LS,
|
|
HI,
|
|
HS,
|
|
EQU,
|
|
NEU,
|
|
LTU,
|
|
LEU,
|
|
GTU,
|
|
GEU,
|
|
NUM,
|
|
// NAN is a MACRO
|
|
NotANumber,
|
|
|
|
BASE_MASK = 0xFF,
|
|
FTZ_FLAG = 0x100
|
|
};
|
|
}
|
|
}
|
|
} // end namespace llvm;
|
|
|
|
// Defines symbolic names for NVPTX registers. This defines a mapping from
|
|
// register name to register number.
|
|
#define GET_REGINFO_ENUM
|
|
#include "NVPTXGenRegisterInfo.inc"
|
|
|
|
// Defines symbolic names for the NVPTX instructions.
|
|
#define GET_INSTRINFO_ENUM
|
|
#include "NVPTXGenInstrInfo.inc"
|
|
|
|
#endif
|