mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228973 91177308-0d34-0410-b5e6-96231b3b80d8
340 lines
11 KiB
C++
340 lines
11 KiB
C++
//===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCTargetTransformInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppctti"
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static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
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cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
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//===----------------------------------------------------------------------===//
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//
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// PPC cost model.
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//
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//===----------------------------------------------------------------------===//
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TargetTransformInfo::PopcntSupportKind
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PPCTTIImpl::getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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if (ST->hasPOPCNTD() && TyWidth <= 64)
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return TTI::PSK_FastHardware;
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return TTI::PSK_Software;
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}
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unsigned PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
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if (DisablePPCConstHoist)
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return BaseT::getIntImmCost(Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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if (Imm == 0)
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return TTI::TCC_Free;
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if (Imm.getBitWidth() <= 64) {
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if (isInt<16>(Imm.getSExtValue()))
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return TTI::TCC_Basic;
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if (isInt<32>(Imm.getSExtValue())) {
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// A constant that can be materialized using lis.
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if ((Imm.getZExtValue() & 0xFFFF) == 0)
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return TTI::TCC_Basic;
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return 2 * TTI::TCC_Basic;
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}
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}
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return 4 * TTI::TCC_Basic;
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}
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unsigned PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty) {
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if (DisablePPCConstHoist)
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return BaseT::getIntImmCost(IID, Idx, Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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switch (IID) {
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default:
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return TTI::TCC_Free;
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::ssub_with_overflow:
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case Intrinsic::usub_with_overflow:
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if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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break;
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case Intrinsic::experimental_stackmap:
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if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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return TTI::TCC_Free;
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break;
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case Intrinsic::experimental_patchpoint_void:
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case Intrinsic::experimental_patchpoint_i64:
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if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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return TTI::TCC_Free;
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break;
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}
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return PPCTTIImpl::getIntImmCost(Imm, Ty);
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}
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unsigned PPCTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx,
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const APInt &Imm, Type *Ty) {
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if (DisablePPCConstHoist)
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return BaseT::getIntImmCost(Opcode, Idx, Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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unsigned ImmIdx = ~0U;
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bool ShiftedFree = false, RunFree = false, UnsignedFree = false,
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ZeroFree = false;
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switch (Opcode) {
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default:
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return TTI::TCC_Free;
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case Instruction::GetElementPtr:
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// Always hoist the base address of a GetElementPtr. This prevents the
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// creation of new constants for every base constant that gets constant
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// folded with the offset.
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if (Idx == 0)
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return 2 * TTI::TCC_Basic;
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return TTI::TCC_Free;
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case Instruction::And:
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RunFree = true; // (for the rotate-and-mask instructions)
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// Fallthrough...
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case Instruction::Add:
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case Instruction::Or:
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case Instruction::Xor:
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ShiftedFree = true;
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// Fallthrough...
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case Instruction::Sub:
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case Instruction::Mul:
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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ImmIdx = 1;
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break;
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case Instruction::ICmp:
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UnsignedFree = true;
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ImmIdx = 1;
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// Fallthrough... (zero comparisons can use record-form instructions)
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case Instruction::Select:
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ZeroFree = true;
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break;
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case Instruction::PHI:
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case Instruction::Call:
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case Instruction::Ret:
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case Instruction::Load:
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case Instruction::Store:
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break;
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}
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if (ZeroFree && Imm == 0)
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return TTI::TCC_Free;
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if (Idx == ImmIdx && Imm.getBitWidth() <= 64) {
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if (isInt<16>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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if (RunFree) {
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if (Imm.getBitWidth() <= 32 &&
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(isShiftedMask_32(Imm.getZExtValue()) ||
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isShiftedMask_32(~Imm.getZExtValue())))
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return TTI::TCC_Free;
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if (ST->isPPC64() &&
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(isShiftedMask_64(Imm.getZExtValue()) ||
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isShiftedMask_64(~Imm.getZExtValue())))
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return TTI::TCC_Free;
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}
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if (UnsignedFree && isUInt<16>(Imm.getZExtValue()))
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return TTI::TCC_Free;
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if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0)
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return TTI::TCC_Free;
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}
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return PPCTTIImpl::getIntImmCost(Imm, Ty);
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}
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void PPCTTIImpl::getUnrollingPreferences(Loop *L,
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TTI::UnrollingPreferences &UP) {
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if (ST->getDarwinDirective() == PPC::DIR_A2) {
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// The A2 is in-order with a deep pipeline, and concatenation unrolling
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// helps expose latency-hiding opportunities to the instruction scheduler.
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UP.Partial = UP.Runtime = true;
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}
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BaseT::getUnrollingPreferences(L, UP);
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}
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unsigned PPCTTIImpl::getNumberOfRegisters(bool Vector) {
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if (Vector && !ST->hasAltivec())
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return 0;
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return ST->hasVSX() ? 64 : 32;
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}
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unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) {
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if (Vector) {
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if (ST->hasAltivec()) return 128;
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return 0;
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}
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if (ST->isPPC64())
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return 64;
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return 32;
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}
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unsigned PPCTTIImpl::getMaxInterleaveFactor() {
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unsigned Directive = ST->getDarwinDirective();
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// The 440 has no SIMD support, but floating-point instructions
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// have a 5-cycle latency, so unroll by 5x for latency hiding.
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if (Directive == PPC::DIR_440)
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return 5;
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// The A2 has no SIMD support, but floating-point instructions
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// have a 6-cycle latency, so unroll by 6x for latency hiding.
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if (Directive == PPC::DIR_A2)
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return 6;
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// FIXME: For lack of any better information, do no harm...
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if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
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return 1;
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// For P7 and P8, floating-point instructions have a 6-cycle latency and
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// there are two execution units, so unroll by 12x for latency hiding.
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if (Directive == PPC::DIR_PWR7 ||
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Directive == PPC::DIR_PWR8)
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return 12;
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// For most things, modern systems have two execution units (and
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// out-of-order execution).
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return 2;
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}
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unsigned PPCTTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
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TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo,
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TTI::OperandValueProperties Opd2PropInfo) {
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assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
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// Fallback to the default implementation.
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
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Opd1PropInfo, Opd2PropInfo);
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}
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unsigned PPCTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp) {
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return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
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}
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unsigned PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
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assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
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return BaseT::getCastInstrCost(Opcode, Dst, Src);
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}
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unsigned PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) {
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return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy);
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}
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unsigned PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) {
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assert(Val->isVectorTy() && "This must be a vector type");
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
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// Double-precision scalars are already located in index #0.
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if (Index == 0)
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return 0;
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return BaseT::getVectorInstrCost(Opcode, Val, Index);
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}
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// Estimated cost of a load-hit-store delay. This was obtained
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// experimentally as a minimum needed to prevent unprofitable
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// vectorization for the paq8p benchmark. It may need to be
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// raised further if other unprofitable cases remain.
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unsigned LHSPenalty = 2;
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if (ISD == ISD::INSERT_VECTOR_ELT)
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LHSPenalty += 7;
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// Vector element insert/extract with Altivec is very expensive,
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// because they require store and reload with the attendant
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// processor stall for load-hit-store. Until VSX is available,
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// these need to be estimated as very costly.
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if (ISD == ISD::EXTRACT_VECTOR_ELT ||
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ISD == ISD::INSERT_VECTOR_ELT)
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return LHSPenalty + BaseT::getVectorInstrCost(Opcode, Val, Index);
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return BaseT::getVectorInstrCost(Opcode, Val, Index);
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}
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unsigned PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
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unsigned Alignment,
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unsigned AddressSpace) {
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// Legalize the type.
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
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assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
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"Invalid Opcode");
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unsigned Cost = BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
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// VSX loads/stores support unaligned access.
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if (ST->hasVSX()) {
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if (LT.second == MVT::v2f64 || LT.second == MVT::v2i64)
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return Cost;
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}
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bool UnalignedAltivec =
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Src->isVectorTy() &&
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Src->getPrimitiveSizeInBits() >= LT.second.getSizeInBits() &&
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LT.second.getSizeInBits() == 128 &&
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Opcode == Instruction::Load;
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// PPC in general does not support unaligned loads and stores. They'll need
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// to be decomposed based on the alignment factor.
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unsigned SrcBytes = LT.second.getStoreSize();
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if (SrcBytes && Alignment && Alignment < SrcBytes && !UnalignedAltivec) {
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Cost += LT.first*(SrcBytes/Alignment-1);
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// For a vector type, there is also scalarization overhead (only for
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// stores, loads are expanded using the vector-load + permutation sequence,
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// which is much less expensive).
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if (Src->isVectorTy() && Opcode == Instruction::Store)
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for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
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Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);
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}
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return Cost;
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}
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