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6502/llvm-6502
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mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2026-10-22 14:03:16 +00:00
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2bc29dc0bcb3c1441477a062e4a5cffff175c8ca
llvm-6502/test/CodeGen
T
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David Goodwin baeb911d60 Add Thumb-2 support for TEQ amd TST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 22:49:42 +00:00
..
Alpha
…
ARM
Implement Thumb2 ldr.
2009-06-29 07:51:04 +00:00
CBackend
Fix an erroneous check for isFNeg; the FNeg case is handled
2009-06-04 23:43:29 +00:00
CellSPU
Add some generic expansion logic for SMULO and UMULO. Fixes UMULO
2009-06-16 06:58:29 +00:00
CPP
Fix code emission for conditional branches.
2009-05-04 19:10:38 +00:00
Generic
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
IA64
…
Mips
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
MSP430
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
PowerPC
Don't grep the -debug output. This isn't the way to test changes.
2009-06-25 21:59:32 +00:00
SPARC
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
Thumb
We should run these tests as well.
2009-06-24 21:36:26 +00:00
Thumb2
Add Thumb-2 support for TEQ amd TST.
2009-06-29 22:49:42 +00:00
X86
FIX PR 4459.
2009-06-29 20:29:59 +00:00
XCore
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
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