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them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145852 91177308-0d34-0410-b5e6-96231b3b80d8
1085 lines
42 KiB
TableGen
1085 lines
42 KiB
TableGen
//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "MipsInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Mips profiles and nodes
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//===----------------------------------------------------------------------===//
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def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
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def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>,
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SDTCisSameAs<3, 4>,
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SDTCisInt<4>]>;
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def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
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[SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>,
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SDTCisSameAs<2, 3>]>;
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def SDT_MipsDivRem : SDTypeProfile<0, 2,
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[SDTCisInt<0>,
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SDTCisSameAs<0, 1>]>;
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def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
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def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
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SDTCisSameAs<0, 1>]>;
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def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
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SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
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def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
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SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
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SDTCisSameAs<0, 4>]>;
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// Call
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def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
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[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
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SDNPVariadic]>;
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// Hi and Lo nodes are used to handle global addresses. Used on
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// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
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// static model. (nothing to do with Mips Registers Hi and Lo)
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
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// TlsGd node is used to handle General Dynamic TLS
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def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
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// TprelHi and TprelLo nodes are used to handle Local Exec TLS
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def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
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def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
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// Thread pointer
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def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
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// Return
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def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
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SDNPOptInGlue]>;
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// These are target-independent nodes, but have target-specific formats.
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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// MAdd*/MSub* nodes
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def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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// DivRem(u) nodes
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def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
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[SDNPOutGlue]>;
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def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
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[SDNPOutGlue]>;
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// Target constant nodes that are not part of any isel patterns and remain
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// unchanged can cause instructions with illegal operands to be emitted.
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// Wrapper node patterns give the instruction selector a chance to replace
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// target constant nodes that would otherwise remain unchanged with ADDiu
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// nodes. Without these wrapper node patterns, the following conditional move
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// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
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// compiled:
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// movn %got(d)($gp), %got(c)($gp), $4
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// This instruction is illegal since movn can take only register operands.
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def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>;
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// Pointer to dynamically allocated stack area.
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def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
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[SDNPHasChain, SDNPInGlue]>;
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def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
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def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
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def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
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def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
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def HasSwap : Predicate<"Subtarget.hasSwap()">;
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def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
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def HasMips32 : Predicate<"Subtarget.hasMips32()">;
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def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
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def HasMips64 : Predicate<"Subtarget.hasMips64()">;
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def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
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def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
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def IsN64 : Predicate<"Subtarget.isABI_N64()">;
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def NotN64 : Predicate<"!Subtarget.isABI_N64()">;
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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def jmptarget : Operand<OtherVT> {
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let EncoderMethod = "getJumpTargetOpValue";
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}
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def brtarget : Operand<OtherVT> {
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let EncoderMethod = "getBranchTargetOpValue";
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let OperandType = "OPERAND_PCREL";
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}
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def calltarget : Operand<iPTR> {
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let EncoderMethod = "getJumpTargetOpValue";
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}
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def calltarget64: Operand<i64>;
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def simm16 : Operand<i32>;
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def simm16_64 : Operand<i64>;
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def shamt : Operand<i32>;
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// Unsigned Operand
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def uimm16 : Operand<i32> {
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let PrintMethod = "printUnsignedImm";
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}
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// Address operand
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def mem : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPURegs, simm16);
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let EncoderMethod = "getMemEncoding";
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}
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def mem64 : Operand<i64> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPU64Regs, simm16_64);
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}
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def mem_ea : Operand<i32> {
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let PrintMethod = "printMemOperandEA";
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let MIOperandInfo = (ops CPURegs, simm16);
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let EncoderMethod = "getMemEncoding";
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}
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def mem_ea_64 : Operand<i64> {
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let PrintMethod = "printMemOperandEA";
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let MIOperandInfo = (ops CPU64Regs, simm16_64);
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let EncoderMethod = "getMemEncoding";
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}
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// size operand of ext instruction
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def size_ext : Operand<i32> {
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let EncoderMethod = "getSizeExtEncoding";
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}
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// size operand of ins instruction
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def size_ins : Operand<i32> {
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let EncoderMethod = "getSizeInsEncoding";
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}
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// Transformation Function - get the lower 16 bits.
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def LO16 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
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}]>;
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// Transformation Function - get the higher 16 bits.
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def HI16 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getZExtValue() >> 16);
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}]>;
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// Node immediate fits as 16-bit sign extended on target immediate.
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// e.g. addi, andi
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def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
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// Node immediate fits as 16-bit zero extended on target immediate.
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// The LO16 param means that only the lower 16 bits of the node
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// immediate are caught.
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// e.g. addiu, sltiu
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def immZExt16 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32)
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return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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else
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return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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}], LO16>;
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// shamt field must fit in 5 bits.
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def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
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//===----------------------------------------------------------------------===//
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// Pattern fragment for load/store
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//===----------------------------------------------------------------------===//
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class UnalignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
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LoadSDNode *LD = cast<LoadSDNode>(N);
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return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
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}]>;
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class AlignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
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LoadSDNode *LD = cast<LoadSDNode>(N);
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return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
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}]>;
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class UnalignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
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(Node node:$val, node:$ptr), [{
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StoreSDNode *SD = cast<StoreSDNode>(N);
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return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
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}]>;
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class AlignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
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(Node node:$val, node:$ptr), [{
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StoreSDNode *SD = cast<StoreSDNode>(N);
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return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
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}]>;
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// Load/Store PatFrags.
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def sextloadi16_a : AlignedLoad<sextloadi16>;
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def zextloadi16_a : AlignedLoad<zextloadi16>;
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def extloadi16_a : AlignedLoad<extloadi16>;
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def load_a : AlignedLoad<load>;
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def sextloadi32_a : AlignedLoad<sextloadi32>;
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def zextloadi32_a : AlignedLoad<zextloadi32>;
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def extloadi32_a : AlignedLoad<extloadi32>;
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def truncstorei16_a : AlignedStore<truncstorei16>;
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def store_a : AlignedStore<store>;
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def truncstorei32_a : AlignedStore<truncstorei32>;
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def sextloadi16_u : UnalignedLoad<sextloadi16>;
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def zextloadi16_u : UnalignedLoad<zextloadi16>;
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def extloadi16_u : UnalignedLoad<extloadi16>;
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def load_u : UnalignedLoad<load>;
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def sextloadi32_u : UnalignedLoad<sextloadi32>;
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def zextloadi32_u : UnalignedLoad<zextloadi32>;
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def extloadi32_u : UnalignedLoad<extloadi32>;
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def truncstorei16_u : UnalignedStore<truncstorei16>;
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def store_u : UnalignedStore<store>;
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def truncstorei32_u : UnalignedStore<truncstorei32>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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// Arithmetic and logical instructions with 3 register operands.
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class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
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FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"),
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[(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
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let shamt = 0;
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let isCommutable = isComm;
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}
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class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
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InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
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FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
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let shamt = 0;
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let isCommutable = isComm;
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}
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// Arithmetic and logical instructions with 2 register operands.
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class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type, RegisterClass RC> :
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FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
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!strconcat(instr_asm, "\t$rt, $rs, $imm16"),
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[(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu>;
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class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type, RegisterClass RC> :
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FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
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!strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
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class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
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FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
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!strconcat(instr_asm, "\t$rs, $rt"),
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[(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
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let rd = 0;
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let shamt = 0;
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let isCommutable = isComm;
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}
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// Logical
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class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
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FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"),
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[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
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let shamt = 0;
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let isCommutable = 1;
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}
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// Shifts
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class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
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SDNode OpNode, PatFrag PF, Operand ImmOpnd,
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RegisterClass RC>:
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FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
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!strconcat(instr_asm, "\t$rd, $rt, $shamt"),
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[(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
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let rs = isRotate;
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}
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// 32-bit shift instructions.
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class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
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SDNode OpNode>:
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shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
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class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
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SDNode OpNode, RegisterClass RC>:
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FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rt, $rs"),
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[(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
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let shamt = isRotate;
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}
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// Load Upper Imediate
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class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
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FI<op, (outs RC:$rt), (ins Imm:$imm16),
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!strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
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let rs = 0;
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}
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class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
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bits<21> addr;
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let Inst{25-21} = addr{20-16};
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let Inst{15-0} = addr{15-0};
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}
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// Memory Load/Store
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let canFoldAsLoad = 1 in
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class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
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Operand MemOpnd, bit Pseudo>:
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FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
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!strconcat(instr_asm, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addr:$addr))], IILoad> {
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let isPseudo = Pseudo;
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}
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class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
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Operand MemOpnd, bit Pseudo>:
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FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
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!strconcat(instr_asm, "\t$rt, $addr"),
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[(OpNode RC:$rt, addr:$addr)], IIStore> {
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let isPseudo = Pseudo;
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}
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// Memory Load/Store
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let canFoldAsLoad = 1 in
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class LoadX<bits<6> op, RegisterClass RC,
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Operand MemOpnd>:
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FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
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"",
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[], IILoad> {
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}
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class StoreX<bits<6> op, RegisterClass RC,
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Operand MemOpnd>:
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FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
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"",
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[], IIStore> {
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}
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// 32-bit load.
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multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
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bit Pseudo = 0> {
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def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
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Requires<[NotN64]>;
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def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
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Requires<[IsN64]>;
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}
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|
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// 64-bit load.
|
|
multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
|
|
bit Pseudo = 0> {
|
|
def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
|
|
Requires<[NotN64]>;
|
|
def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
|
|
Requires<[IsN64]>;
|
|
}
|
|
|
|
// 32-bit load.
|
|
multiclass LoadX32<bits<6> op> {
|
|
def #NAME# : LoadX<op, CPURegs, mem>,
|
|
Requires<[NotN64]>;
|
|
def _P8 : LoadX<op, CPURegs, mem64>,
|
|
Requires<[IsN64]>;
|
|
}
|
|
// 32-bit store.
|
|
multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
|
|
bit Pseudo = 0> {
|
|
def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
|
|
Requires<[NotN64]>;
|
|
def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
|
|
Requires<[IsN64]>;
|
|
}
|
|
|
|
// 64-bit store.
|
|
multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
|
|
bit Pseudo = 0> {
|
|
def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
|
|
Requires<[NotN64]>;
|
|
def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
|
|
Requires<[IsN64]>;
|
|
}
|
|
|
|
// 32-bit store.
|
|
multiclass StoreX32<bits<6> op> {
|
|
def #NAME# : StoreX<op, CPURegs, mem>,
|
|
Requires<[NotN64]>;
|
|
def _P8 : StoreX<op, CPURegs, mem64>,
|
|
Requires<[IsN64]>;
|
|
}
|
|
|
|
// Conditional Branch
|
|
class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
|
|
CBranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
|
|
!strconcat(instr_asm, "\t$rs, $rt, $imm16"),
|
|
[(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
|
|
let isBranch = 1;
|
|
let isTerminator = 1;
|
|
let hasDelaySlot = 1;
|
|
}
|
|
|
|
class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
|
|
RegisterClass RC>:
|
|
CBranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
|
|
!strconcat(instr_asm, "\t$rs, $imm16"),
|
|
[(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
|
|
let rt = _rt;
|
|
let isBranch = 1;
|
|
let isTerminator = 1;
|
|
let hasDelaySlot = 1;
|
|
}
|
|
|
|
// SetCC
|
|
class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
|
|
RegisterClass RC>:
|
|
FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
|
|
!strconcat(instr_asm, "\t$rd, $rs, $rt"),
|
|
[(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
|
|
IIAlu> {
|
|
let shamt = 0;
|
|
}
|
|
|
|
class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
|
|
PatLeaf imm_type, RegisterClass RC>:
|
|
FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
|
|
!strconcat(instr_asm, "\t$rt, $rs, $imm16"),
|
|
[(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
|
|
IIAlu>;
|
|
|
|
// Unconditional branch
|
|
let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
|
|
class JumpFJ<bits<6> op, string instr_asm>:
|
|
FJ<op, (outs), (ins jmptarget:$target),
|
|
!strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
|
|
|
|
let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,
|
|
isIndirectBranch = 1 in
|
|
class JumpFR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
|
|
FR<op, func, (outs), (ins RC:$rs),
|
|
!strconcat(instr_asm, "\t$rs"), [(brind RC:$rs)], IIBranch> {
|
|
let rt = 0;
|
|
let rd = 0;
|
|
let shamt = 0;
|
|
}
|
|
|
|
// Jump and Link (Call)
|
|
let isCall=1, hasDelaySlot=1,
|
|
// All calls clobber the non-callee saved registers...
|
|
Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
|
|
K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
|
|
class JumpLink<bits<6> op, string instr_asm>:
|
|
FJ<op, (outs), (ins calltarget:$target, variable_ops),
|
|
!strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
|
|
IIBranch>;
|
|
|
|
class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
|
|
FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
|
|
!strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch> {
|
|
let rt = 0;
|
|
let rd = 31;
|
|
let shamt = 0;
|
|
}
|
|
|
|
class BranchLink<string instr_asm>:
|
|
FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$imm16, variable_ops),
|
|
!strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>;
|
|
}
|
|
|
|
// Mul, Div
|
|
class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
|
|
RegisterClass RC, list<Register> DefRegs>:
|
|
FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
|
|
!strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
|
|
let rd = 0;
|
|
let shamt = 0;
|
|
let isCommutable = 1;
|
|
let Defs = DefRegs;
|
|
}
|
|
|
|
class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
|
|
Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
|
|
|
|
class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
|
|
RegisterClass RC, list<Register> DefRegs>:
|
|
FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
|
|
!strconcat(instr_asm, "\t$$zero, $rs, $rt"),
|
|
[(op RC:$rs, RC:$rt)], itin> {
|
|
let rd = 0;
|
|
let shamt = 0;
|
|
let Defs = DefRegs;
|
|
}
|
|
|
|
class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
|
|
Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
|
|
|
|
// Move from Hi/Lo
|
|
class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
|
|
list<Register> UseRegs>:
|
|
FR<0x00, func, (outs RC:$rd), (ins),
|
|
!strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
|
|
let rs = 0;
|
|
let rt = 0;
|
|
let shamt = 0;
|
|
let Uses = UseRegs;
|
|
}
|
|
|
|
class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
|
|
list<Register> DefRegs>:
|
|
FR<0x00, func, (outs), (ins RC:$rs),
|
|
!strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
|
|
let rt = 0;
|
|
let rd = 0;
|
|
let shamt = 0;
|
|
let Defs = DefRegs;
|
|
}
|
|
|
|
class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
|
|
FMem<0x09, (outs RC:$rt), (ins Mem:$addr),
|
|
instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>;
|
|
|
|
// Count Leading Ones/Zeros in Word
|
|
class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
|
|
FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
|
|
!strconcat(instr_asm, "\t$rd, $rs"),
|
|
[(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
|
|
Requires<[HasBitCount]> {
|
|
let shamt = 0;
|
|
let rt = rd;
|
|
}
|
|
|
|
class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
|
|
FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
|
|
!strconcat(instr_asm, "\t$rd, $rs"),
|
|
[(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
|
|
Requires<[HasBitCount]> {
|
|
let shamt = 0;
|
|
let rt = rd;
|
|
}
|
|
|
|
// Sign Extend in Register.
|
|
class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt>:
|
|
FR<0x1f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt),
|
|
!strconcat(instr_asm, "\t$rd, $rt"),
|
|
[(set CPURegs:$rd, (sext_inreg CPURegs:$rt, vt))], NoItinerary> {
|
|
let rs = 0;
|
|
let shamt = sa;
|
|
let Predicates = [HasSEInReg];
|
|
}
|
|
|
|
// Byte Swap
|
|
class ByteSwap<bits<6> func, bits<5> sa, string instr_asm>:
|
|
FR<0x1f, func, (outs CPURegs:$rd), (ins CPURegs:$rt),
|
|
!strconcat(instr_asm, "\t$rd, $rt"),
|
|
[(set CPURegs:$rd, (bswap CPURegs:$rt))], NoItinerary> {
|
|
let rs = 0;
|
|
let shamt = sa;
|
|
let Predicates = [HasSwap];
|
|
}
|
|
|
|
// Read Hardware
|
|
class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd),
|
|
"rdhwr\t$rt, $rd", [], IIAlu> {
|
|
let rs = 0;
|
|
let shamt = 0;
|
|
}
|
|
|
|
// Ext and Ins
|
|
class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
|
|
FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
|
|
!strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
|
|
[(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
|
|
bits<5> pos;
|
|
bits<5> sz;
|
|
let rd = sz;
|
|
let shamt = pos;
|
|
let Predicates = [HasMips32r2];
|
|
}
|
|
|
|
class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
|
|
FR<0x1f, _funct, (outs RC:$rt),
|
|
(ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
|
|
!strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
|
|
[(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
|
|
NoItinerary> {
|
|
bits<5> pos;
|
|
bits<5> sz;
|
|
let rd = sz;
|
|
let shamt = pos;
|
|
let Predicates = [HasMips32r2];
|
|
let Constraints = "$src = $rt";
|
|
}
|
|
|
|
// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
|
|
class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
|
|
RegisterClass PRC> :
|
|
MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
|
|
!strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
|
|
[(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
|
|
|
|
multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
|
|
def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, Requires<[NotN64]>;
|
|
def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, Requires<[IsN64]>;
|
|
}
|
|
|
|
// Atomic Compare & Swap.
|
|
class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
|
|
RegisterClass PRC> :
|
|
MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
|
|
!strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
|
|
[(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
|
|
|
|
multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
|
|
def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, Requires<[NotN64]>;
|
|
def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, Requires<[IsN64]>;
|
|
}
|
|
|
|
class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
|
|
FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
|
|
!strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
|
|
FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
|
|
!strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
|
|
let mayStore = 1;
|
|
let Constraints = "$rt = $dst";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// As stack alignment is always done with addiu, we need a 16-bit immediate
|
|
let Defs = [SP], Uses = [SP] in {
|
|
def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
|
|
"!ADJCALLSTACKDOWN $amt",
|
|
[(callseq_start timm:$amt)]>;
|
|
def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
|
|
"!ADJCALLSTACKUP $amt1",
|
|
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
|
}
|
|
|
|
// Some assembly macros need to avoid pseudoinstructions and assembler
|
|
// automatic reodering, we should reorder ourselves.
|
|
def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
|
|
def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
|
|
def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
|
|
def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
|
|
|
|
// These macros are inserted to prevent GAS from complaining
|
|
// when using the AT register.
|
|
def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
|
|
def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
|
|
|
|
// When handling PIC code the assembler needs .cpload and .cprestore
|
|
// directives. If the real instructions corresponding these directives
|
|
// are used, we have the same behavior, but get also a bunch of warnings
|
|
// from the assembler.
|
|
def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
|
|
def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
|
|
|
|
let usesCustomInserter = 1 in {
|
|
defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
|
|
defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
|
|
defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
|
|
defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
|
|
defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
|
|
defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
|
|
defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
|
|
defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
|
|
defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
|
|
defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
|
|
defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
|
|
defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
|
|
defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
|
|
defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
|
|
defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
|
|
defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
|
|
defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
|
|
defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
|
|
|
|
defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
|
|
defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
|
|
defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
|
|
|
|
defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
|
|
defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
|
|
defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction definition
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MipsI Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Arithmetic Instructions (ALU Immediate)
|
|
def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
|
|
def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
|
|
def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
|
|
def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
|
|
def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
|
|
def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
|
|
def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
|
|
def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
|
|
|
|
/// Arithmetic Instructions (3-Operand, R-Type)
|
|
def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
|
|
def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
|
|
def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
|
|
def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
|
|
def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
|
|
def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
|
|
def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
|
|
def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
|
|
def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
|
|
def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
|
|
|
|
/// Shift Instructions
|
|
def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
|
|
def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
|
|
def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
|
|
def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
|
|
def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
|
|
def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
|
|
|
|
// Rotate Instructions
|
|
let Predicates = [HasMips32r2] in {
|
|
def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
|
|
def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
|
|
}
|
|
|
|
/// Load and Store Instructions
|
|
/// aligned
|
|
defm LB : LoadM32<0x20, "lb", sextloadi8>;
|
|
defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
|
|
defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
|
|
defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
|
|
defm LW : LoadM32<0x23, "lw", load_a>;
|
|
defm SB : StoreM32<0x28, "sb", truncstorei8>;
|
|
defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
|
|
defm SW : StoreM32<0x2b, "sw", store_a>;
|
|
|
|
/// unaligned
|
|
defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
|
|
defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
|
|
defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
|
|
defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
|
|
defm USW : StoreM32<0x2b, "usw", store_u, 1>;
|
|
|
|
/// Primitives for unaligned
|
|
defm LWL : LoadX32<0x22>;
|
|
defm LWR : LoadX32<0x26>;
|
|
defm SWL : StoreX32<0x2A>;
|
|
defm SWR : StoreX32<0x2E>;
|
|
|
|
let hasSideEffects = 1 in
|
|
def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
|
|
[(MipsSync imm:$stype)], NoItinerary, FrmOther>
|
|
{
|
|
bits<5> stype;
|
|
let Opcode = 0;
|
|
let Inst{25-11} = 0;
|
|
let Inst{10-6} = stype;
|
|
let Inst{5-0} = 15;
|
|
}
|
|
|
|
/// Load-linked, Store-conditional
|
|
def LL : LLBase<0x30, "ll", CPURegs, mem>, Requires<[NotN64]>;
|
|
def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, Requires<[IsN64]>;
|
|
def SC : SCBase<0x38, "sc", CPURegs, mem>, Requires<[NotN64]>;
|
|
def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>;
|
|
|
|
/// Jump and Branch Instructions
|
|
def J : JumpFJ<0x02, "j">;
|
|
def JR : JumpFR<0x00, 0x08, "jr", CPURegs>;
|
|
def JAL : JumpLink<0x03, "jal">;
|
|
def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
|
|
def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
|
|
def BNE : CBranch<0x05, "bne", setne, CPURegs>;
|
|
def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
|
|
def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
|
|
def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
|
|
def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
|
|
|
|
let rt=0x11 in
|
|
def BGEZAL : BranchLink<"bgezal">;
|
|
let rt=0x10 in
|
|
def BLTZAL : BranchLink<"bltzal">;
|
|
|
|
let isReturn=1, isTerminator=1, hasDelaySlot=1,
|
|
isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
|
|
def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
|
|
"jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
|
|
|
|
/// Multiply and Divide Instructions.
|
|
def MULT : Mult32<0x18, "mult", IIImul>;
|
|
def MULTu : Mult32<0x19, "multu", IIImul>;
|
|
def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
|
|
def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
|
|
|
|
def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
|
|
def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
|
|
def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
|
|
def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
|
|
|
|
/// Sign Ext In Register Instructions.
|
|
def SEB : SignExtInReg<0x10, "seb", i8>;
|
|
def SEH : SignExtInReg<0x18, "seh", i16>;
|
|
|
|
/// Count Leading
|
|
def CLZ : CountLeading0<0x20, "clz", CPURegs>;
|
|
def CLO : CountLeading1<0x21, "clo", CPURegs>;
|
|
|
|
/// Byte Swap
|
|
def WSBW : ByteSwap<0x20, 0x2, "wsbw">;
|
|
|
|
/// No operation
|
|
let addr=0 in
|
|
def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
|
|
|
|
// FrameIndexes are legalized when they are operands from load/store
|
|
// instructions. The same not happens for stack address copies, so an
|
|
// add op with mem ComplexPattern is used and the stack address copy
|
|
// can be matched. It's similar to Sparc LEA_ADDRi
|
|
def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
|
|
|
|
// DynAlloc node points to dynamically allocated stack space.
|
|
// $sp is added to the list of implicitly used registers to prevent dead code
|
|
// elimination from removing instructions that modify $sp.
|
|
let Uses = [SP] in
|
|
def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
|
|
|
|
// MADD*/MSUB*
|
|
def MADD : MArithR<0, "madd", MipsMAdd, 1>;
|
|
def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
|
|
def MSUB : MArithR<4, "msub", MipsMSub>;
|
|
def MSUBU : MArithR<5, "msubu", MipsMSubu>;
|
|
|
|
// MUL is a assembly macro in the current used ISAs. In recent ISA's
|
|
// it is a real instruction.
|
|
def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
|
|
Requires<[HasMips32]>;
|
|
|
|
def RDHWR : ReadHardware;
|
|
|
|
def EXT : ExtBase<0, "ext", CPURegs>;
|
|
def INS : InsBase<4, "ins", CPURegs>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arbitrary patterns that map to one or more instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Small immediates
|
|
def : Pat<(i32 immSExt16:$in),
|
|
(ADDiu ZERO, imm:$in)>;
|
|
def : Pat<(i32 immZExt16:$in),
|
|
(ORi ZERO, imm:$in)>;
|
|
|
|
// Arbitrary immediates
|
|
def : Pat<(i32 imm:$imm),
|
|
(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
|
|
|
// Carry patterns
|
|
def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
|
|
(SUBu CPURegs:$lhs, CPURegs:$rhs)>;
|
|
def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
|
|
(ADDu CPURegs:$lhs, CPURegs:$rhs)>;
|
|
def : Pat<(addc CPURegs:$src, immSExt16:$imm),
|
|
(ADDiu CPURegs:$src, imm:$imm)>;
|
|
|
|
// Call
|
|
def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
|
|
(JAL tglobaladdr:$dst)>;
|
|
def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
|
|
(JAL texternalsym:$dst)>;
|
|
//def : Pat<(MipsJmpLink CPURegs:$dst),
|
|
// (JALR CPURegs:$dst)>;
|
|
|
|
// hi/lo relocs
|
|
def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
|
|
def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
|
|
def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
|
|
def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
|
|
|
|
def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
|
|
def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
|
|
def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
|
|
def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
|
|
|
|
def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
|
|
(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
|
|
def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
|
|
(ADDiu CPURegs:$hi, tblockaddress:$lo)>;
|
|
def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
|
|
(ADDiu CPURegs:$hi, tjumptable:$lo)>;
|
|
def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
|
|
(ADDiu CPURegs:$hi, tconstpool:$lo)>;
|
|
|
|
// gp_rel relocs
|
|
def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
|
|
(ADDiu CPURegs:$gp, tglobaladdr:$in)>;
|
|
def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
|
|
(ADDiu CPURegs:$gp, tconstpool:$in)>;
|
|
|
|
// tlsgd
|
|
def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)),
|
|
(ADDiu CPURegs:$gp, tglobaltlsaddr:$in)>;
|
|
|
|
// tprel hi/lo
|
|
def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
|
|
def : Pat<(MipsTprelLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
|
|
def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)),
|
|
(ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
|
|
|
|
// wrapper_pic
|
|
class WrapperPICPat<SDNode node>:
|
|
Pat<(MipsWrapperPIC node:$in),
|
|
(ADDiu GP, node:$in)>;
|
|
|
|
def : WrapperPICPat<tglobaladdr>;
|
|
def : WrapperPICPat<tconstpool>;
|
|
def : WrapperPICPat<texternalsym>;
|
|
def : WrapperPICPat<tblockaddress>;
|
|
def : WrapperPICPat<tjumptable>;
|
|
|
|
// Mips does not have "not", so we expand our way
|
|
def : Pat<(not CPURegs:$in),
|
|
(NOR CPURegs:$in, ZERO)>;
|
|
|
|
// extended load and stores
|
|
def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
|
|
def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
|
|
def : Pat<(extloadi16_a addr:$src), (LHu addr:$src)>;
|
|
def : Pat<(extloadi16_u addr:$src), (ULHu addr:$src)>;
|
|
|
|
// peepholes
|
|
def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
|
|
|
|
// brcond patterns
|
|
multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
|
|
Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
|
|
Instruction SLTiuOp, Register ZEROReg> {
|
|
def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
|
|
(BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
|
|
def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
|
|
(BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
|
|
|
|
def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
|
|
(BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
|
|
def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
|
|
(BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
|
|
def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
|
|
(BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
|
def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
|
|
(BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
|
|
|
def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
|
|
(BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
|
|
def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
|
|
(BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
|
|
|
|
def : Pat<(brcond RC:$cond, bb:$dst),
|
|
(BNEOp RC:$cond, ZEROReg, bb:$dst)>;
|
|
}
|
|
|
|
defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
|
|
|
|
// setcc patterns
|
|
multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
|
|
Instruction SLTuOp, Register ZEROReg> {
|
|
def : Pat<(seteq RC:$lhs, RC:$rhs),
|
|
(SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
|
|
def : Pat<(setne RC:$lhs, RC:$rhs),
|
|
(SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
|
|
}
|
|
|
|
multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
|
def : Pat<(setle RC:$lhs, RC:$rhs),
|
|
(XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
|
|
def : Pat<(setule RC:$lhs, RC:$rhs),
|
|
(XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
|
|
}
|
|
|
|
multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
|
def : Pat<(setgt RC:$lhs, RC:$rhs),
|
|
(SLTOp RC:$rhs, RC:$lhs)>;
|
|
def : Pat<(setugt RC:$lhs, RC:$rhs),
|
|
(SLTuOp RC:$rhs, RC:$lhs)>;
|
|
}
|
|
|
|
multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
|
def : Pat<(setge RC:$lhs, RC:$rhs),
|
|
(XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
|
|
def : Pat<(setuge RC:$lhs, RC:$rhs),
|
|
(XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
|
|
}
|
|
|
|
multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
|
|
Instruction SLTiuOp> {
|
|
def : Pat<(setge RC:$lhs, immSExt16:$rhs),
|
|
(XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
|
|
def : Pat<(setuge RC:$lhs, immSExt16:$rhs),
|
|
(XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
|
|
}
|
|
|
|
defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
|
|
defm : SetlePats<CPURegs, SLT, SLTu>;
|
|
defm : SetgtPats<CPURegs, SLT, SLTu>;
|
|
defm : SetgePats<CPURegs, SLT, SLTu>;
|
|
defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
|
|
|
|
// select MipsDynAlloc
|
|
def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "MipsInstrFPU.td"
|
|
include "Mips64InstrInfo.td"
|
|
include "MipsCondMov.td"
|
|
|