llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00

History

Gerolf Hoflehner 2bddd7cf65 [AAarch64] Optimize CSINC-branch sequence Peephole optimization that generates a single conditional branch for csinc-branch sequences like in the examples below. This is possible when the csinc sets or clears a register based on a condition code and the branch checks that register. Also the condition code may not be modified between the csinc and the original branch. Examples: 1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44 to b.<invCC> 2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44 to b.<CC> rdar://problem/18506500 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219742 91177308-0d34-0410-b5e6-96231b3b80d8	2014-10-14 23:07:53 +00:00
..
llvm	[AAarch64] Optimize CSINC-branch sequence	2014-10-14 23:07:53 +00:00
llvm-c	Introduce LLVMWriteBitcodeToMemoryBuffer C API function.	2014-10-14 00:30:59 +00:00

Gerolf Hoflehner 2bddd7cf65 [AAarch64] Optimize CSINC-branch sequence

Peephole optimization that generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the csinc and the original branch.

Examples:

1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44
   to b.<invCC>

2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44
   to b.<CC>


rdar://problem/18506500



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219742 91177308-0d34-0410-b5e6-96231b3b80d8

2014-10-14 23:07:53 +00:00

llvm

[AAarch64] Optimize CSINC-branch sequence

2014-10-14 23:07:53 +00:00

llvm-c

Introduce LLVMWriteBitcodeToMemoryBuffer C API function.

2014-10-14 00:30:59 +00:00