Quentin Colombet 28a24ca471 [ARM64] Fix the information we give to the peephole optimizer for comparison. ... ANDS does not use the same encoding scheme as other xxxS instructions (e.g., ADDS). Take that into account to avoid wrong peephole optimization. <rdar://problem/16693089> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207020 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-23 20:43:38 +00:00
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AArch64	AArch64/ARM64: more testing from AArch64 to ARM64	2014-04-22 12:45:47 +00:00
ARM	Fix test/CodeGen/arm.ll	2014-04-23 01:09:29 +00:00
ARM64	[ARM64] Fix the information we give to the peephole optimizer for comparison.	2014-04-23 20:43:38 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX	Fix the test: DCE optimized away everything.	2014-04-21 17:23:12 +00:00
PowerPC
R600	R600: Add a test that used to be broken that I forgot to add	2014-04-23 19:45:05 +00:00
SPARC	Revert "blockfreq: Temporarily turn on -debug-only=block-freq"	2014-04-19 22:45:44 +00:00
SystemZ
Thumb
Thumb2
X86	AVX-512: store and truncstore for i1 values	2014-04-22 14:13:10 +00:00
XCore	Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-21 17:57:07 +00:00