Tim Northover 2c0d42ac9a ARM: do not generate BLX instructions on Cortex-M CPUs. ... Particularly on MachO, we were generating "blx _dest" instructions on M-class CPUs, which don't actually exist. They happen to get fixed up by the linker into valid "bl _dest" instructions (which is why such a massive issue has remained largely undetected), but we shouldn't rely on that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214959 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-06 11:13:14 +00:00
..
Analysis	Teach the SLP Vectorizer that keeping some values live over a callsite can have a cost.	2014-08-05 12:30:34 +00:00
AsmParser	Remove dead code in condition	2014-08-05 18:22:58 +00:00
Bitcode	BitcodeReader: Fix non-determinism in use-list order	2014-08-05 17:49:48 +00:00
CodeGen	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
DebugInfo
ExecutionEngine
IR	Provide convenient access to the zext/sext attributes of function arguments. NFC.	2014-08-05 05:43:41 +00:00
IRReader
LineEditor
Linker
LTO	Don't internalize all but main by default.	2014-08-05 20:10:38 +00:00
MC
Object
Option
ProfileData
Support
TableGen	Allow binary and for tblgen math.	2014-08-05 09:43:25 +00:00
Target	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
Transforms	[dfsan] Try not to create too many additional basic blocks in functions which	2014-08-06 00:33:40 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile