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5ac065a797
mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176917 91177308-0d34-0410-b5e6-96231b3b80d8
131 lines
4.7 KiB
C++
131 lines
4.7 KiB
C++
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Mips target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsTargetMachine.h"
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#include "Mips.h"
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#include "MipsFrameLowering.h"
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#include "MipsInstrInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeMipsTarget() {
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// Register the target.
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RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
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RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
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RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
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RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
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}
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// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
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// The stack is always 8 byte aligned
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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// offset from the stack/frame pointer, using StackGrowsUp enables
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// an easier handling.
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// Using CodeModel::Large enables different CALL behavior.
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MipsTargetMachine::
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MipsTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool isLittle)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, isLittle, RM),
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DL(isLittle ?
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(Subtarget.isABI_N64() ?
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"e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-"
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"n32:64-S128" :
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"e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64") :
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(Subtarget.isABI_N64() ?
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"E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-"
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"n32:64-S128" :
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"E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64")),
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InstrInfo(MipsInstrInfo::create(*this)),
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FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
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TLInfo(MipsTargetLowering::create(*this)), TSInfo(*this), JITInfo() {
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}
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void MipsebTargetMachine::anchor() { }
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MipsebTargetMachine::
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MipsebTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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void MipselTargetMachine::anchor() { }
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MipselTargetMachine::
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MipselTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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namespace {
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/// Mips Code Generator Pass Configuration Options.
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class MipsPassConfig : public TargetPassConfig {
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public:
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MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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MipsTargetMachine &getMipsTargetMachine() const {
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return getTM<MipsTargetMachine>();
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}
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const MipsSubtarget &getMipsSubtarget() const {
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return *getMipsTargetMachine().getSubtargetImpl();
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}
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virtual bool addInstSelector();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new MipsPassConfig(this, PM);
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}
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsPassConfig::addInstSelector() {
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addPass(createMipsISelDag(getMipsTargetMachine()));
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return false;
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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bool MipsPassConfig::addPreEmitPass() {
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MipsTargetMachine &TM = getMipsTargetMachine();
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addPass(createMipsDelaySlotFillerPass(TM));
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// NOTE: long branch has not been implemented for mips16.
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if (TM.getSubtarget<MipsSubtarget>().hasStandardEncoding())
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addPass(createMipsLongBranchPass(TM));
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if (TM.getSubtarget<MipsSubtarget>().inMips16Mode())
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addPass(createMipsConstantIslandPass(TM));
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return true;
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}
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bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE) {
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// Machine code emitter pass for Mips.
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PM.add(createMipsJITCodeEmitterPass(*this, JCE));
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return false;
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}
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