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https://github.com/c64scene-ar/llvm-6502.git
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73e44d8ae4
In reality, some unaligned memory accesses are legal for 32-bit types and smaller too, but it all depends on the address space. Allowing unaligned loads/stores for > 32-bit types is mainly to prevent the legalizer from splitting one load into multiple loads of smaller types. https://bugs.freedesktop.org/show_bug.cgi?id=65873 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184822 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
2.0 KiB
LLVM
49 lines
2.0 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
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; floating-point store
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; EG-CHECK: @store_f32
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; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1
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; CM-CHECK: @store_f32
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; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @store_f32
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; SI-CHECK: BUFFER_STORE_DWORD
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define void @store_f32(float addrspace(1)* %out, float %in) {
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store float %in, float addrspace(1)* %out
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ret void
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}
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; The stores in this function are combined by the optimizer to create a
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; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
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; should not try to split the 64-bit store back into 2 32-bit stores.
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;
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; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
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; be two 32-bit stores.
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; EG-CHECK: @vecload2
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; EG-CHECK: RAT_WRITE_CACHELESS_32_eg
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; EG-CHECK: RAT_WRITE_CACHELESS_32_eg
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; CM-CHECK: @vecload2
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; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
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; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
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; SI-CHECK: @vecload2
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; SI-CHECK: BUFFER_STORE_DWORDX2
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define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
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entry:
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%0 = load i32 addrspace(2)* %mem, align 4, !tbaa !5
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%arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
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%1 = load i32 addrspace(2)* %arrayidx1.i, align 4, !tbaa !5
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store i32 %0, i32 addrspace(1)* %out, align 4, !tbaa !5
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%arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
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store i32 %1, i32 addrspace(1)* %arrayidx1, align 4, !tbaa !5
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!5 = metadata !{metadata !"int", metadata !6}
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!6 = metadata !{metadata !"omnipotent char", metadata !7}
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!7 = metadata !{metadata !"Simple C/C++ TBAA"}
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