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2c6363a62d
Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8 |
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Analysis | ||
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AsmParser | ||
Bitcode | ||
CodeGen | ||
CompilerDriver | ||
ExecutionEngine | ||
Linker | ||
MC | ||
Object | ||
Support | ||
Target | ||
Transforms | ||
VMCore | ||
CMakeLists.txt | ||
Makefile |