mirror of
https://github.com/c64scene-ar/llvm-6502.git
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the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
498 lines
22 KiB
C++
498 lines
22 KiB
C++
//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the target machine instruction set to the code generator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#include "llvm/Target/TargetInstrDesc.h"
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#include "llvm/CodeGen/MachineFunction.h"
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namespace llvm {
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class TargetAsmInfo;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class LiveVariables;
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class CalleeSavedInfo;
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class SDNode;
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class SelectionDAG;
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template<class T> class SmallVectorImpl;
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//---------------------------------------------------------------------------
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///
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/// TargetInstrInfo - Interface to description of machine instruction set
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///
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class TargetInstrInfo {
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const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
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unsigned NumOpcodes; // Number of entries in the desc array
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
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virtual ~TargetInstrInfo();
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// Invariant opcodes: All instruction sets have these as their low opcodes.
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enum {
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PHI = 0,
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INLINEASM = 1,
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DBG_LABEL = 2,
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EH_LABEL = 3,
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GC_LABEL = 4,
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DECLARE = 5,
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/// EXTRACT_SUBREG - This instruction takes two operands: a register
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/// that has subregisters, and a subregister index. It returns the
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/// extracted subregister value. This is commonly used to implement
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/// truncation operations on target architectures which support it.
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EXTRACT_SUBREG = 6,
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/// INSERT_SUBREG - This instruction takes three operands: a register
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/// that has subregisters, a register providing an insert value, and a
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/// subregister index. It returns the value of the first register with
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/// the value of the second register inserted. The first register is
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/// often defined by an IMPLICIT_DEF, as is commonly used to implement
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/// anyext operations on target architectures which support it.
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INSERT_SUBREG = 7,
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/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
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IMPLICIT_DEF = 8,
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/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except
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/// that the first operand is an immediate integer constant. This constant
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/// is often zero, as is commonly used to implement zext operations on
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/// target architectures which support it, such as with x86-64 (with
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/// zext from i32 to i64 via implicit zero-extension).
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SUBREG_TO_REG = 9,
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/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
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/// register-to-register copy into a specific register class. This is only
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/// used between instruction selection and MachineInstr creation, before
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/// virtual registers have been created for all the instructions, and it's
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/// only needed in cases where the register classes implied by the
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/// instructions are insufficient. The actual MachineInstrs to perform
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/// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
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COPY_TO_REGCLASS = 10
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};
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unsigned getNumOpcodes() const { return NumOpcodes; }
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const TargetInstrDesc &get(unsigned Opcode) const {
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assert(Opcode < NumOpcodes && "Invalid opcode!");
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return Descriptors[Opcode];
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}
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/// isTriviallyReMaterializable - Return true if the instruction is trivially
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/// rematerializable, meaning it has no side effects and requires no operands
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/// that aren't always available.
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bool isTriviallyReMaterializable(const MachineInstr *MI) const {
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return MI->getDesc().isRematerializable() &&
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isReallyTriviallyReMaterializable(MI);
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}
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protected:
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/// isReallyTriviallyReMaterializable - For instructions with opcodes for
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/// which the M_REMATERIALIZABLE flag is set, this function tests whether the
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/// instruction itself is actually trivially rematerializable, considering
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/// its operands. This is used for targets that have instructions that are
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/// only trivially rematerializable for specific uses. This predicate must
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/// return false if the instruction has any side effects other than
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/// producing a value, or if it requres any address registers that are not
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/// always available.
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virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
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return true;
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}
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public:
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/// Return true if the instruction is a register to register move and return
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/// the source and dest operands and their sub-register indices by reference.
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& SrcReg, unsigned& DstReg,
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unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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return 0;
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}
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/// reMaterialize - Re-issue the specified 'original' instruction at the
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/// specific location targeting a new destination register.
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virtual void reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig) const = 0;
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/// isInvariantLoad - Return true if the specified instruction (which is
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/// marked mayLoad) is loading from a location whose value is invariant across
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/// the function. For example, loading a value from the constant pool or from
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/// from the argument area of a function if it does not change. This should
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/// only return true of *all* loads the instruction does are invariant (if it
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/// does multiple loads).
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virtual bool isInvariantLoad(const MachineInstr *MI) const {
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return false;
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}
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into one or more true
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/// three-address instructions on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the last new instruction.
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///
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virtual MachineInstr *
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convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
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return 0;
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}
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/// commuteInstruction - If a target has any instructions that are commutable,
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/// but require converting to a different instruction or making non-trivial
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/// changes to commute them, this method can overloaded to do this. The
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/// default implementation of this method simply swaps the first two operands
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/// of MI and returns it.
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///
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/// If a target wants to make more aggressive changes, they can construct and
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/// return a new machine instruction. If an instruction cannot commute, it
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/// can also return null.
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///
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/// If NewMI is true, then a new machine instruction must be created.
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///
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virtual MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI = false) const = 0;
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/// findCommutedOpIndices - If specified MI is commutable, return the two
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/// operand indices that would swap value. Return true if the instruction
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/// is not in a form which this routine understands.
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virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const = 0;
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/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with an conditional branch and it falls through to
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/// an successor block, it sets TBB to be the branch destination block and
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/// a list of operands that evaluate the condition. These
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/// operands can be passed to other TargetInstrInfo methods to create new
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/// branches.
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/// 4. If this block ends with an conditional branch and an unconditional
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/// block, it returns the 'true' destination in TBB, the 'false'
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/// destination in FBB, and a list of operands that evaluate the condition.
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/// These operands can be passed to other TargetInstrInfo methods to create
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/// new branches.
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///
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/// Note that RemoveBranch and InsertBranch must be implemented to support
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/// cases where this method returns success.
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///
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/// If AllowModify is true, then this routine is allowed to modify the basic
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/// block (e.g. delete instructions after the unconditional branch).
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///
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const {
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return true;
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}
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/// RemoveBranch - Remove the branching code at the end of the specific MBB.
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/// This is only invoked in cases where AnalyzeBranch returns success. It
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/// returns the number of instructions that were removed.
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
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assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
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return 0;
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}
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/// InsertBranch - Insert a branch into the end of the specified
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/// MachineBasicBlock. This operands to this method are the same as those
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/// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
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/// returns success and when an unconditional branch (TBB is non-null, FBB is
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/// null, Cond is empty) needs to be inserted. It returns the number of
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/// instructions inserted.
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///
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/// It is also invoked by tail merging to add unconditional branches in
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/// cases where AnalyzeBranch doesn't apply because there was no original
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/// branch to analyze. At least this much must be implemented, else tail
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/// merging needs to be disabled.
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
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return 0;
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}
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/// copyRegToReg - Emit instructions to copy between a pair of registers. It
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/// returns false if the target does not how to copy between the specified
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/// registers.
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
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return false;
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}
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/// storeRegToStackSlot - Store the specified register of the given register
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/// class to the specified stack frame index. The store instruction is to be
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/// added to the given machine basic block before the specified machine
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/// instruction. If isKill is true, the register operand is the last use and
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/// must be marked kill.
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const {
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assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
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}
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/// loadRegFromStackSlot - Load the specified register of the given register
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/// class from the specified stack frame index. The load instruction is to be
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/// added to the given machine basic block before the specified machine
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/// instruction.
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const {
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assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
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}
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/// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
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/// saved registers and returns true if it isn't possible / profitable to do
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/// so by issuing a series of store instructions via
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/// storeRegToStackSlot(). Returns false otherwise.
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virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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return false;
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}
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/// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
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/// saved registers and returns true if it isn't possible / profitable to do
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/// so by issuing a series of load instructions via loadRegToStackSlot().
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/// Returns false otherwise.
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virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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return false;
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}
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/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
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/// slot into the specified machine instruction for the specified operand(s).
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/// If this is possible, a new instruction is returned with the specified
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/// operand folded, otherwise NULL is returned. The client is responsible for
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/// removing the old instruction and adding the new one in the instruction
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/// stream.
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MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const;
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protected:
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/// foldMemoryOperandImpl - Target-dependent implementation for
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/// foldMemoryOperand. Target-independent code in foldMemoryOperand will
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/// take care of adding a MachineMemOperand to the newly created instruction.
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const {
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return 0;
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}
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/// foldMemoryOperandImpl - Target-dependent implementation for
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/// foldMemoryOperand. Target-independent code in foldMemoryOperand will
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/// take care of adding a MachineMemOperand to the newly created instruction.
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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return 0;
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}
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public:
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/// canFoldMemoryOperand - Returns true for the specified load / store if
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/// folding is possible.
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virtual
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bool canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const {
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return false;
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}
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/// unfoldMemoryOperand - Separate a single instruction which folded a load or
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/// a store or a load and a store into two or more instruction. If this is
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/// possible, returns true as well as the new instructions by reference.
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virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
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SmallVectorImpl<MachineInstr*> &NewMIs) const{
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return false;
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}
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virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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SmallVectorImpl<SDNode*> &NewNodes) const {
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return false;
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}
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/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
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/// instruction after load / store are unfolded from an instruction of the
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/// specified opcode. It returns zero if the specified unfolding is not
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/// possible.
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virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
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bool UnfoldLoad, bool UnfoldStore) const {
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return 0;
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}
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/// BlockHasNoFallThrough - Return true if the specified block does not
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/// fall-through into its successor block. This is primarily used when a
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/// branch is unanalyzable. It is useful for things like unconditional
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/// indirect branches (jump tables).
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virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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return false;
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}
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/// ReverseBranchCondition - Reverses the branch condition of the specified
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/// condition list, returning false on success and true if it cannot be
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/// reversed.
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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return true;
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}
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/// insertNoop - Insert a noop into the instruction stream at the specified
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/// point.
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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/// isPredicated - Returns true if the instruction is already predicated.
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///
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virtual bool isPredicated(const MachineInstr *MI) const {
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return false;
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}
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/// isUnpredicatedTerminator - Returns true if the instruction is a
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/// terminator instruction that has not been predicated.
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virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
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/// PredicateInstruction - Convert the instruction into a predicated
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/// instruction. It returns true if the operation was successful.
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const = 0;
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/// SubsumesPredicate - Returns true if the first specified predicate
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/// subsumes the second, e.g. GE subsumes GT.
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const {
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return false;
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}
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/// DefinesPredicate - If the specified instruction defines any predicate
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/// or condition code register(s) used for predication, returns true as well
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/// as the definition predicate(s) by reference.
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const {
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return false;
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}
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/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
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/// instruction that defines the specified register class.
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virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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return true;
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}
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/// isDeadInstruction - Return true if the instruction is considered dead.
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/// This allows some late codegen passes to delete them.
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virtual bool isDeadInstruction(const MachineInstr *MI) const = 0;
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/// GetInstSize - Returns the size of the specified Instruction.
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///
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virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
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assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
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return 0;
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}
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/// GetFunctionSizeInBytes - Returns the size of the specified
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/// MachineFunction.
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///
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virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
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/// Measure the specified inline asm to determine an approximation of its
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/// length.
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virtual unsigned getInlineAsmLength(const char *Str,
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const TargetAsmInfo &TAI) const;
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};
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/// TargetInstrInfoImpl - This is the default implementation of
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/// TargetInstrInfo, which just provides a couple of default implementations
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/// for various methods. This separated out because it is implemented in
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/// libcodegen, not in libtarget.
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class TargetInstrInfoImpl : public TargetInstrInfo {
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protected:
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TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
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: TargetInstrInfo(desc, NumOpcodes) {}
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public:
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virtual MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI = false) const;
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virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const;
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virtual bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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virtual void reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubReg,
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const MachineInstr *Orig) const;
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virtual bool isDeadInstruction(const MachineInstr *MI) const;
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virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
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};
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} // End llvm namespace
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#endif
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