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563a9cf7ba
For two intrinsics 'llvm.nvvm.texsurf.handle' and 'llvm.nvvm.texsurf.handle.internal',
TableGen was emitting matching code like:
if (Name.startswith("llvm.nvvm.texsurf.handle")) ...
if (Name.startswith("llvm.nvvm.texsurf.handle.internal")) ...
We can never match "llvm.nvvm.texsurf.handle.internal" here because it will
always be erroneously matched by the first condition.
The fix is to sort the intrinsic names and emit them in reverse order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187119 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
915 B
TableGen
36 lines
915 B
TableGen
// RUN: llvm-tblgen -gen-intrinsic %s | FileCheck %s
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class IntrinsicProperty;
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class ValueType<int size, int value> {
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string Namespace = "MVT";
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int Size = size;
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int Value = value;
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}
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class LLVMType<ValueType vt> {
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ValueType VT = vt;
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}
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class Intrinsic<string name, list<LLVMType> param_types = []> {
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string LLVMName = name;
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bit isTarget = 0;
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string TargetPrefix = "";
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list<LLVMType> RetTypes = [];
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list<LLVMType> ParamTypes = param_types;
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list<IntrinsicProperty> Properties = [];
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}
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def iAny : ValueType<0, 254>;
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def llvm_anyint_ty : LLVMType<iAny>;
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// Make sure an intrinsic name that is a prefix of another is checked after the
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// other.
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// CHECK: if (NameR.startswith("oo.bar.")) return Intrinsic::foo_bar;
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// CHECK: if (NameR.startswith("oo.")) return Intrinsic::foo;
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def int_foo : Intrinsic<"llvm.foo", [llvm_anyint_ty]>;
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def int_foo_bar : Intrinsic<"llvm.foo.bar", [llvm_anyint_ty]>;
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