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The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203204 91177308-0d34-0410-b5e6-96231b3b80d8
551 lines
20 KiB
C++
551 lines
20 KiB
C++
//===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips32/64 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEFrameLowering.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsMachineFunction.h"
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#include "MipsSEInstrInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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namespace {
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typedef MachineBasicBlock::iterator Iter;
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static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) {
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if (Mips::ACC64RegClass.contains(Src))
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return std::make_pair((unsigned)Mips::PseudoMFHI,
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(unsigned)Mips::PseudoMFLO);
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if (Mips::ACC64DSPRegClass.contains(Src))
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return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
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if (Mips::ACC128RegClass.contains(Src))
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return std::make_pair((unsigned)Mips::PseudoMFHI64,
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(unsigned)Mips::PseudoMFLO64);
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return std::make_pair(0, 0);
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}
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/// Helper class to expand pseudos.
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class ExpandPseudo {
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public:
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ExpandPseudo(MachineFunction &MF);
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bool expand();
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private:
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bool expandInstr(MachineBasicBlock &MBB, Iter I);
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void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
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void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
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void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
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void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
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unsigned MFLoOpc, unsigned RegSize);
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bool expandCopy(MachineBasicBlock &MBB, Iter I);
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bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
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unsigned MFLoOpc);
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MachineFunction &MF;
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MachineRegisterInfo &MRI;
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};
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}
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ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
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: MF(MF_), MRI(MF.getRegInfo()) {}
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bool ExpandPseudo::expand() {
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bool Expanded = false;
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for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
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BB != BBEnd; ++BB)
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for (Iter I = BB->begin(), End = BB->end(); I != End;)
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Expanded |= expandInstr(*BB, I++);
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return Expanded;
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}
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bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
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switch(I->getOpcode()) {
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case Mips::LOAD_CCOND_DSP:
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expandLoadCCond(MBB, I);
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break;
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case Mips::STORE_CCOND_DSP:
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expandStoreCCond(MBB, I);
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break;
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case Mips::LOAD_ACC64:
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case Mips::LOAD_ACC64DSP:
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expandLoadACC(MBB, I, 4);
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break;
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case Mips::LOAD_ACC128:
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expandLoadACC(MBB, I, 8);
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break;
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case Mips::STORE_ACC64:
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expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
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break;
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case Mips::STORE_ACC64DSP:
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expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
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break;
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case Mips::STORE_ACC128:
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expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
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break;
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case TargetOpcode::COPY:
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if (!expandCopy(MBB, I))
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return false;
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break;
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default:
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return false;
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}
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MBB.erase(I);
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return true;
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}
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void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
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// load $vr, FI
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// copy ccond, $vr
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const TargetRegisterClass *RC = RegInfo.intRegClass(4);
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unsigned VR = MRI.createVirtualRegister(RC);
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unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
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BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
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.addReg(VR, RegState::Kill);
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}
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void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
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// copy $vr, ccond
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// store $vr, FI
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const TargetRegisterClass *RC = RegInfo.intRegClass(4);
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unsigned VR = MRI.createVirtualRegister(RC);
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unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
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.addReg(Src, getKillRegState(I->getOperand(0).isKill()));
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TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
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}
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void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
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unsigned RegSize) {
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// load $vr0, FI
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// copy lo, $vr0
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// load $vr1, FI + 4
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// copy hi, $vr1
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
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unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
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DebugLoc DL = I->getDebugLoc();
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const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
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TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
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BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
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TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
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BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
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}
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void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
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unsigned MFHiOpc, unsigned MFLoOpc,
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unsigned RegSize) {
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// mflo $vr0, src
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// store $vr0, FI
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// mfhi $vr1, src
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// store $vr1, FI + 4
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
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DebugLoc DL = I->getDebugLoc();
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BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
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TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
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BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
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TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
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}
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bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
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unsigned Src = I->getOperand(1).getReg();
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std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
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if (!Opcodes.first)
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return false;
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return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
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}
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bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
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unsigned MFHiOpc, unsigned MFLoOpc) {
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// mflo $vr0, src
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// copy dst_lo, $vr0
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// mfhi $vr1, src
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// copy dst_hi, $vr1
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
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unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
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const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
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unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
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unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
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DebugLoc DL = I->getDebugLoc();
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BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
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BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
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.addReg(VR0, RegState::Kill);
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BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
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BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
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.addReg(VR1, RegState::Kill);
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return true;
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}
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unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const {
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static const unsigned EhDataReg[] = {
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Mips::A0, Mips::A1, Mips::A2, Mips::A3
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};
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static const unsigned EhDataReg64[] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
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};
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return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
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}
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void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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// First, compute final stack size.
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uint64_t StackSize = MFI->getStackSize();
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->adjustsStack()) return;
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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MachineLocation DstML, SrcML;
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// Adjust stack.
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TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
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// emit ".cfi_def_cfa_offset StackSize"
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.size()) {
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// Find the instruction past the last instruction that saves a callee-saved
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// register to the stack.
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for (unsigned i = 0; i < CSI.size(); ++i)
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++MBBI;
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// Iterate over list of callee-saved registers and emit .cfi_offset
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// directives.
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
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unsigned Reg = I->getReg();
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// If Reg is a double precision register, emit two cfa_offsets,
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// one for each of the paired single precision registers.
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if (Mips::AFGR64RegClass.contains(Reg)) {
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unsigned Reg0 =
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MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
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unsigned Reg1 =
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MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
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if (!STI.isLittle())
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std::swap(Reg0, Reg1);
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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} else {
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// Reg is either in GPR32 or FGR32.
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unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
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nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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}
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}
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if (MipsFI->callsEhReturn()) {
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const TargetRegisterClass *RC = STI.isABI_N64() ?
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&Mips::GPR64RegClass : &Mips::GPR32RegClass;
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// Insert instructions that spill eh data registers.
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for (int I = 0; I < 4; ++I) {
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if (!MBB.isLiveIn(ehDataReg(I)))
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MBB.addLiveIn(ehDataReg(I));
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TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
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MipsFI->getEhDataRegFI(I), RC, &RegInfo);
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}
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// Emit .cfi_offset directives for eh data registers.
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for (int I = 0; I < 4; ++I) {
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int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
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unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, Reg, Offset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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}
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// if framepointer enabled, set it to point to the stack pointer.
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if (hasFP(MF)) {
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// Insert instruction "move $fp, $sp" at this location.
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BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
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// emit ".cfi_def_cfa_register $fp"
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unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
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nullptr, MRI->getDwarfRegNum(FP, true)));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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}
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void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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// if framepointer enabled, restore the stack pointer.
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if (hasFP(MF)) {
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// Find the first instruction that restores a callee-saved register.
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MachineBasicBlock::iterator I = MBBI;
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for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
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--I;
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// Insert instruction "move $sp, $fp" at this location.
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BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
|
|
}
|
|
|
|
if (MipsFI->callsEhReturn()) {
|
|
const TargetRegisterClass *RC = STI.isABI_N64() ?
|
|
&Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
|
|
|
// Find first instruction that restores a callee-saved register.
|
|
MachineBasicBlock::iterator I = MBBI;
|
|
for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
|
|
--I;
|
|
|
|
// Insert instructions that restore eh data registers.
|
|
for (int J = 0; J < 4; ++J) {
|
|
TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
|
|
RC, &RegInfo);
|
|
}
|
|
}
|
|
|
|
// Get the number of bytes from FrameInfo
|
|
uint64_t StackSize = MFI->getStackSize();
|
|
|
|
if (!StackSize)
|
|
return;
|
|
|
|
// Adjust stack.
|
|
TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
|
|
}
|
|
|
|
bool MipsSEFrameLowering::
|
|
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI,
|
|
const TargetRegisterInfo *TRI) const {
|
|
MachineFunction *MF = MBB.getParent();
|
|
MachineBasicBlock *EntryBlock = MF->begin();
|
|
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
|
|
|
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
|
// Add the callee-saved register as live-in. Do not add if the register is
|
|
// RA and return address is taken, because it has already been added in
|
|
// method MipsTargetLowering::LowerRETURNADDR.
|
|
// It's killed at the spill, unless the register is RA and return address
|
|
// is taken.
|
|
unsigned Reg = CSI[i].getReg();
|
|
bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
|
|
&& MF->getFrameInfo()->isReturnAddressTaken();
|
|
if (!IsRAAndRetAddrIsTaken)
|
|
EntryBlock->addLiveIn(Reg);
|
|
|
|
// Insert the spill to the stack frame.
|
|
bool IsKill = !IsRAAndRetAddrIsTaken;
|
|
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
|
|
TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
|
|
CSI[i].getFrameIdx(), RC, TRI);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
// Reserve call frame if the size of the maximum call frame fits into 16-bit
|
|
// immediate field and there are no variable sized objects on the stack.
|
|
// Make sure the second register scavenger spill slot can be accessed with one
|
|
// instruction.
|
|
return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) &&
|
|
!MFI->hasVarSizedObjects();
|
|
}
|
|
|
|
// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
|
|
void MipsSEFrameLowering::
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
const MipsSEInstrInfo &TII =
|
|
*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
|
|
|
|
if (!hasReservedCallFrame(MF)) {
|
|
int64_t Amount = I->getOperand(0).getImm();
|
|
|
|
if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
|
|
Amount = -Amount;
|
|
|
|
unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
|
|
TII.adjustStackPtr(SP, Amount, MBB, I);
|
|
}
|
|
|
|
MBB.erase(I);
|
|
}
|
|
|
|
void MipsSEFrameLowering::
|
|
processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
RegScavenger *RS) const {
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
|
|
|
|
// Mark $fp as used if function has dedicated frame pointer.
|
|
if (hasFP(MF))
|
|
MRI.setPhysRegUsed(FP);
|
|
|
|
// Create spill slots for eh data registers if function calls eh_return.
|
|
if (MipsFI->callsEhReturn())
|
|
MipsFI->createEhDataRegsFI();
|
|
|
|
// Expand pseudo instructions which load, store or copy accumulators.
|
|
// Add an emergency spill slot if a pseudo was expanded.
|
|
if (ExpandPseudo(MF).expand()) {
|
|
// The spill slot should be half the size of the accumulator. If target is
|
|
// mips64, it should be 64-bit, otherwise it should be 32-bt.
|
|
const TargetRegisterClass *RC = STI.hasMips64() ?
|
|
&Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
|
int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
|
|
RC->getAlignment(), false);
|
|
RS->addScavengingFrameIndex(FI);
|
|
}
|
|
|
|
// Set scavenging frame index if necessary.
|
|
uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
|
|
estimateStackSize(MF);
|
|
|
|
if (isInt<16>(MaxSPOffset))
|
|
return;
|
|
|
|
const TargetRegisterClass *RC = STI.isABI_N64() ?
|
|
&Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
|
int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
|
|
RC->getAlignment(), false);
|
|
RS->addScavengingFrameIndex(FI);
|
|
}
|
|
|
|
const MipsFrameLowering *
|
|
llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
|
|
return new MipsSEFrameLowering(ST);
|
|
}
|